ECE Lab #6: Operational Amplifiers: Part 1

Department of Electrical and Computer Engineering

Spring 2026 (Note: Acknowledgment: The lab was derived from Simple Op Amps, For ADALM2000 by Doug Mercer)

Overview

The purpose of Lab 6 is to:

1. Prelab Assignment

Action item: Read Appendix A (Circuit Construction and Debugging) before the lab session.

1.1 AI Exploration: Op-Amp Concepts and Limits

Objective: Use an AI assistant to build a working mental model of the LMC662 and the circuits in this lab before working through any calculations. Students who complete this section first find the calculation deliverables significantly easier. Completing it after the calculations defeats the purpose.

Focus Area 1: Slew Rate vs. Gain-Bandwidth Product

Example prompts are provided below. You may use them, adapt them, or write your own at the same level of specificity.

"Can you explain the difference between gain-bandwidth product and slew rate in an op-amp? One describes a small-signal frequency limit and the other a large-signal rate-of-change limit, but I am not sure which is which or what causes each one physically."

Follow up with:

"How can slew rate cause the output of a voltage follower to look different from the input, even though the closed-loop gain is unity? Give me a concrete numerical example."

Focus Area 2: The Loading Problem and Why It Matters

"I have a voltage divider with two 4.7 k$\Omega$ resistors. When I connect a 1 k$\Omega$ load across the lower resistor, the voltage I measure is much lower than the unloaded value. Can you explain physically why this happens? What does the voltage follower do to fix it, and what property of the ideal op-amp makes the fix work?"

Self-Test

Using any AI assistant, write your own quiz prompt targeting the two concepts above. Your questions must involve at least one of the following: predicting whether a given signal will trigger slew-rate limiting in the LMC662, applying the Golden Rules to predict the output of the voltage follower, or explaining why the loading effect changes $V_{in}$ rather than just $V_{out}$ in Buffer Circuit 3.

Apply the meta-prompt from A Mind Worth Questioning (introduced in Module 1) to evaluate and strengthen your draft before running the quiz. Submit your original draft, the AI's critique, your revised prompt, and the full quiz transcript.

Formal Reflection (150--250 words)

Your written synthesis must address all three of the following points:

Prelab Deliverable #1

Submit your formal written reflection (150--250 words, continuous prose) addressing all three points: The Link, The Technical "Why", and The Lab Application.

1.2 LMC662 Device Specifications

Read Appendix B (The LMC662 Operational Amplifier) at the end of this document, then open the LMC662 datasheet. For each deliverable below, state the value with units and answer the question in one sentence.

Prelab Deliverable #2(a)

What is the gain-bandwidth product of the LMC662? State the value with units and in one sentence explain what it means for the maximum bandwidth of the circuits you will build in Lab 6.

Prelab Deliverable #2(b)

What is the slew rate of the LMC662? State the value with units and in one sentence explain what this means for the signals you will observe in Lab 6.

Prelab Deliverable #2(c)

What is the supply voltage range of the LMC662? State the minimum and maximum supply voltage and in one sentence explain why the M2K $\pm$ 5 V supply is appropriate for this lab.

Prelab Deliverable #2(d)

What is the CMRR of the LMC662 in dB? In one sentence, explain what this number means for a signal that appears identically on both op-amp inputs.

Prelab Deliverable #2(e)

What is the PSRR of the LMC662 in dB? In one sentence, explain what this number means for fluctuations on the power supply rails.

1.3 Gain-Bandwidth Product

Op-Amp Frequency Behavior with Negative Feedback

The Open-Loop Starting Point

A real op-amp does not have infinite gain at all frequencies. Its open-loop gain $A_{OL}(f)$ is huge at DC (typically $10^5$ to $10^6$) but rolls off at high frequencies. For an internally compensated op-amp, the magnitude response looks like a single-pole low-pass filter:

$$A_{OL}(f) = \frac{A_0}{1 + j(f/f_p)}$$

where $A_0$ is the DC open-loop gain and $f_p$ is the open-loop pole (often just a few Hz). Above $f_p$, the gain falls at 20 dB per decade.

Gain-Bandwidth Product

Because the roll-off is 20 dB/decade, the product of gain and frequency stays constant along that slope:

$$\text{GBW} = A_0 \cdot f_p = f_T$$

GBW (also called the unity-gain frequency $f_T$) is the frequency at which the open-loop gain has fallen to 1 (0 dB). For reference, a 741 has GBW around 1 MHz; the LMC662 you are using has GBW = 1.4 MHz.

What Negative Feedback Does

When you close the loop with a resistor network, you set a closed-loop gain $G_{CL}$ that depends only on the resistor ratio, not on the op-amp itself, as long as the op-amp has open-loop gain to spare. For a non-inverting amplifier:

$$G_{CL} = 1 + \frac{R_f}{R_g}$$

The closed-loop response stays flat at $G_{CL}$ until the op-amp runs out of open-loop gain. Beyond that point the closed-loop response is forced to follow the open-loop curve downward.

The $-3$ dB Bandwidth

The $-3$ dB bandwidth of the closed-loop amplifier is the frequency where the open-loop curve intersects $G_{CL}$:

$$f_{-3\,\text{dB}} = \frac{\text{GBW}}{G_{CL}}$$

This is the fundamental trade-off: gain costs you bandwidth, one for one.

Worked Example

For an op-amp with GBW = 1 MHz:

Signals beyond $f_{-3\,\text{dB}}$ are no longer amplified by $G_{CL}$. The output rolls off at 20 dB per decade and the circuit behaves increasingly like the bare op-amp.

Practical Takeaways

The closed-loop gain set by your resistors is only valid in the flat region below $f_{-3\,\text{dB}}$. Always check that your signal frequencies fall inside that window. GBW is fixed by the op-amp you choose, so selecting a faster part is the only way to push $f_{-3\,\text{dB}}$ out without giving up gain.

Prelab Deliverable #3(a)

Using the LMC662 GBW from Deliverable #2(a), calculate $f_{-3\,\text{dB}}$ at a closed-loop gain of 1. Show your work on paper. Photograph your work and submit the image. Your name must be visible in the photo.

Prelab Deliverable #3(b)

Calculate the maximum $-3$ dB bandwidth of the LMC662 at a closed-loop gain of 10. Show your work on paper. Photograph your work and submit the image. Your name must be visible in the photo.

Prelab Deliverable #3(c)

Calculate the maximum $-3$ dB bandwidth of the LMC662 at a closed-loop gain of 100. Show your work on paper. Photograph your work and submit the image. Your name must be visible in the photo.

Prelab Deliverable #3(d)

In one sentence, explain why gain and bandwidth trade off in this way for an amplifier with a fixed gain-bandwidth product.

1.4 Slew Rate

Prelab Deliverable #4(a)

A square wave drives a voltage follower input, producing a 10 V output step. Using the LMC662 slew rate from Deliverable #2(b), calculate the minimum rise time of the output. Show your work on paper. Photograph your work and submit the image. Your name must be visible in the photo.

Prelab Deliverable #4(b)

At what square wave frequency would the rise time from Deliverable #4(a) equal approximately 10% of the half-period? Show all steps on paper. Photograph your work and submit the image. Your name must be visible in the photo.

1.5 Voltage Follower Analysis

Apply the Golden Rules to the voltage follower circuit shown below.

Circuit diagram of a unity-gain buffer, also called a voltage follower, using op-amp OA. A sinusoidal voltage source connects from ground to the input node Vin, which is also probed by Channel 2 oscilloscope. The Vin node connects to the non-inverting input pin 3 of op-amp OA. The output pin 1 connects to node Vout which is probed by Channel 1 oscilloscope to ground. A direct feedback wire connects the output pin 1 back to the inverting input pin 2, creating 100 percent negative feedback that makes the output voltage equal to the input voltage. The circuit demonstrates that the op-amp output can drive a load without drawing current from the source.

Figure 2: Unity-gain buffer (voltage follower) circuit.

Prelab Deliverable #5(a)

State the two Golden Rules of ideal op-amp analysis and the condition under which they apply. Then use them to derive the output voltage of the voltage follower in terms of the input voltage. Show all steps on paper. Photograph your work and submit the image. Your name must be visible in the photo.

Prelab Deliverable #5(b)

In one sentence, explain why the voltage follower has effectively infinite input resistance.

Prelab Deliverable #5(c)

In one sentence, explain why the voltage follower has effectively zero output resistance.

1.6 Buffer Loading Calculations

The circuit in the Unity-Gain Buffer section of this lab uses a voltage divider built from two 4.7 k$\Omega$ resistors driven by a sinusoidal source. The output of the lower resistor is the node labeled $V_{in}$ to the op-amp.

Prelab Deliverable #6(a)

No buffer is present; a 10 k$\Omega$ load connects directly across the lower 4.7 k$\Omega$ resistor of the divider. Calculate the expected amplitude of $V_{in}$ as a fraction of $V_{source}$. Show the equivalent resistance at each step on paper. Photograph your work and submit the image. Your name must be visible in the photo.

Prelab Deliverable #6(b)

Replace the 10 k$\Omega$ load with a 1 k$\Omega$ load across the lower 4.7 k$\Omega$ resistor. Calculate the expected amplitude of $V_{in}$ as a fraction of $V_{source}$. Show the equivalent resistance at each step on paper. Photograph your work and submit the image. Your name must be visible in the photo.

Prelab Deliverable #6(c)

A 1 k$\Omega$ resistor is now placed in parallel with the lower 4.7 k$\Omega$ resistor of the divider (Buffer Circuit 3 topology). Calculate the resulting parallel resistance and the new value of $V_{in}$ as a fraction of $V_{source}$. Show all steps on paper. Photograph your work and submit the image. Your name must be visible in the photo.

1.7 M2K Power Supply Setup

Prelab Deliverable #7(a)

Referring to Appendix B (Section B.4) and the Scopy documentation, describe the steps to configure the M2K power supplies to $+5$ V and $-5$ V in Scopy.

Prelab Deliverable #7(b)

Identify which physical M2K terminals provide $V^+$, $V^-$, and GND.

Prelab Deliverable #7(c)

State which LMC662 pins each M2K terminal connects to. Identify which figure in Appendix B shows the required decoupling capacitor placement.

2. Lab Procedure: Connecting DC Power

Op amps must always be supplied with DC power and therefore it is best to configure these connections first before adding any other circuit components. Figure 1 shows one possible power arrangement on your solderless breadboard. We use two of the long rails for the positive and negative supply voltages, and two others for any ground connections that may be required. Included are the so-called "supply de-coupling" capacitors connected between the power-supply and ground rails. It is too early to discuss in great detail the purpose of these capacitors, but they are used to reduce noise on the supply lines and avoid parasitic oscillations. It is considered good practice in analog circuit design to always include small bypass capacitors close to the supply pins of each op amp in your circuit. Use the side cutters available in the lab to make the wires are cut to as short as possible such that components are flat on the protoboard. Also make the connecting wires such that they are not excessively long.

Power supply breadboard photo showing an LM6134BIN quad op-amp IC inserted across the center divide of a white solderless breadboard. The chip is oriented upside-down relative to the viewer, with pin 1 at the bottom-right. A red jumper wire connects the top power rail to the breadboard row above pin 8 (V+), and a black jumper wire connects the bottom power rail to the row below pin 4 (V−). Two yellow resistors are visible at the top-left and bottom-right corners of the frame. Column numbers 15 through 30 are visible along both edges of the breadboard.

Figure 1: Power supply connections shown for the LM6134 op-amp — not the LMC662 you will use. Apply the same concept to your LMC662: the pin count starts at the indentation (sometimes marked with a dot). For the LMC662, pin 8 is the positive supply ($+5$ V) and pin 4 is the negative supply ($-5$ V). The red arrow indicates the + supply rail, the black the negative supply rail, and the green the ground rails. If you get the power connections wrong, the op-amp will be damaged when voltages are applied. Use red wire for positive, black for negative, and green for ground on your breadboard. Note how the decoupling capacitors are mounted close to the supply pins.

IMPORTANT Leave the power supplies off!! Emphasis: Leave the power supplies off! To be sure, unplug the adaptor board from the M2K for this stage

Get your setup checked off by TA or lab assistant before proceeding to the next step.

Lab Deliverable #1

Once checked off, take a clear photograph of your power supply connections on the breadboard. The photograph must show the ECE Emerge adaptor board so that the connections to the M2K terminals are visible. Make sure the connections are neat and follow the required color coding: red wire for positive supply, black wire for negative supply, and green wire for ground. Your name must be visible in the photo. If you do not use the correct color codes and your wiring is a mess, zero points will be assigned. This is not being picky, it will allow you to trutoubleshoot your cicuits if there is a wiring error. (You will make errors in wiring up circuits - we all do! Knowing how to correct it, that is what differentiates a hobbiest from a professional ECE.)

Lab Deliverable #2

Record the voltage measured at LMC662 pin 8 ($V^+$), including units.

Lab Deliverable #3

Record the voltage measured at LMC662 pin 4 ($V^-$), including units.

IMPORTANT

Leave the power supplies connected to the op-amp in this manner for the next two labs.

3. Lab Procedure: Unity-Gain Amplifier

3.1 Background

The first op-amp circuit is a deceptively simple one, shown in Figure 2. It is known as unity-gain buffer, or sometimes just a voltage follower, defined by the transfer function $\text{V}_{\text{out}}$ = $\text{V}_{\text{in}}$. At first glance it may seem like a useless device, but as we will show later it finds use because of its high input resistance and low output resistance.

3.2 Hardware Setup

Materials

Using the ECE Emerge adaptor board and the ADALM2000 power supplies, construct the circuit shown in Figure 2. Note that the power connections have not been explicitly shown here; it is assumed that those connections must be made in any real circuit (as you did in the previous step), so it is unnecessary to show them in the schematic from this point on. Use jumper wires to connect input and output to the waveform generator and oscilloscope leads.

IMPORTANT

When you are constructing a circuit, turn the power supplies off.

Circuit diagram of a unity-gain buffer, also called a voltage follower, using op-amp OA. A sinusoidal voltage source connects from ground to the input node Vin, which is also probed by Channel 2 oscilloscope. The Vin node connects to the non-inverting input pin 3 of op-amp OA. The output pin 1 connects to node Vout which is probed by Channel 1 oscilloscope to ground. A direct feedback wire connects the output pin 1 back to the inverting input pin 2, creating 100 percent negative feedback that makes the output voltage equal to the input voltage. The circuit demonstrates that the op-amp output can drive a load without drawing current from the source.

Figure 2: Unity-gain buffer (voltage follower) circuit.

3.3 Procedure

Lab Deliverable #4

Screenshot of the oscilloscope display showing the input (CH2) and output (CH1) waveforms at 1 kHz, confirming unity-gain operation. Submit the image via the course submission app. Your name must be visible in the image before uploading.

Scopy oscilloscope screenshot showing the input and output waveforms of a unity-gain voltage follower circuit. The main display shows two overlapping sinusoidal waveforms at 1 kHz: an orange Channel 1 waveform and a purple Channel 2 waveform. The two waveforms are nearly identical in amplitude and phase, confirming that the output follows the input with unity gain and no phase shift. The measurement statistics panel at the top shows Period 999.959 microseconds, Frequency 1.000 kHz, Peak-to-peak 1.953 V, and RMS 681.969 millivolts for Channel 1. The time scale is 1 millisecond per division.

Figure 3: Example oscilloscope waveforms for the unity-gain voltage follower. The orange Channel 1 input and purple Channel 2 output waveforms at 1 kHz are nearly identical in amplitude and phase, confirming unity gain and no phase shift.

Lab Deliverable #5

Take a clear photograph of your unity-gain amplifier circuit on the breadboard. Make sure the connections are neat. Submit the image via the course submission app. Your name must be visible in the photo.

3.4 Slew Rate Limitations

For an ideal op-amp the output will follow the input signal precisely for any input signals, but in a real amplifier the output signal can never respond instantaneously to the input signal. This non-ideality can be observed when the input signal is a rapidly changing function of time. For large-amplitude signals this limitation is quantified by the slew rate, which is the maximum rate-of-change (slope) of the output voltage that the op-amp is capable of delivering. The units of slew-rate are usually expressed as V/$\mu$s.

Diagram illustrating the definition of slew rate using a trapezoidal pulse waveform. The waveform rises from a low level Vmin to a high level Vmax, holds, then falls back to Vmin. Two dashed horizontal reference lines are drawn at 10 percent and 90 percent of the total voltage swing. The rise time Tr is the time for the waveform to travel from the 10 percent level to the 90 percent level on the leading edge, and fall time Tr is similarly marked on the trailing edge. A vertical double-headed arrow shows delta V equals 0.8 times the quantity Vmax minus Vmin, representing the 80 percent voltage swing used to calculate slew rate as delta V divided by Tr.

Figure 4: Slew rate definition. Rise time $T_r$ is measured from the 10% to 90% points of the voltage swing $\Delta V = 0.8(V_{\text{max}} - V_{\text{min}})$, and slew rate is defined as $\Delta V / T_r$.

3.4.1 Procedure

Scopy oscilloscope screenshot showing a rising edge waveform with cursors enabled for slew rate measurement. The main display shows a purple waveform transitioning sharply from a low voltage level on the left to a high voltage level on the right, with the steep rising edge visible near the center of the screen. The cursor measurement panel in the upper left shows delta T of negative 18.502 microseconds, delta V of 1.538 V, and delta of 305.841 millivolts. The Cursors settings panel on the right shows Normal and Track mode buttons with Track selected, and Horizontal and Vertical cursor toggles.

Figure 5: Rising edge measurement using Scopy oscilloscope cursors. Place the horizontal cursors at the 10% and 90% voltage levels and read $\Delta V$ and $\Delta T$ from the cursor panel to calculate slew rate.

$$\text{Slew Rate} = \frac{\Delta V}{T_r}$$

where $\Delta V = 0.8(V_{\text{max}} - V_{\text{min}})$ and $T_r$ is the 10%--90% rise time. Compare your measured value to the LMC662 datasheet specification of 1.1 V/$\mu$s. Note any asymmetry between the rising and falling edge results and suggest a reason.

Lab Deliverable #6

Screenshot of the oscilloscope display showing the slew-rate-limited output with cursors positioned at the 10% and 90% voltage levels. The cursor readout must be visible. Submit the image via the course submission app. Your name must be visible in the image before uploading.

Lab Deliverable #7

From your Lab Deliverable #6 cursor readout, record the measured voltage swing $\Delta V$, including units.

Lab Deliverable #8

Record the measured 10%--90% rise time $T_r$, including units.

Lab Deliverable #9

Record the measured 90%--10% fall time $T_f$, including units.

Lab Deliverable #10

Record the peak-to-peak output voltage, including units.

4. Lab Procedure: M2K MATLAB Control

So far, you have been using Scopy to interface with the M2K hardware. In the final project, you will control the M2K directly from MATLAB using the M2K class.

This section will demonstrate how to control the M2K hardware using the M2K class in MATLAB. You should find the functionality of the M2K class familiar, as it performs the same operations you previously executed in Scopy.

IMPORTANT

Before using MATLAB to control the M2K, make sure the Scopy application is turned off!

4.1 Setup

  1. Include SignalLab.m in your working directory.

  2. Download M2K.m

  3. Place the file in your working MATLAB folder, or add its location permanently to the MATLAB path:

addpath('C:/path/to/folder/containing/M2K')
savepath
  1. Verify that MATLAB can find the class:
which M2K

MATLAB should respond with the full path to M2K.m. If it does not, confirm that the file is in the correct folder and that addpath was run successfully.

  1. Consult M2K MATLAB Class — User Guide

  2. Install the libm2k library and test the programming environment by following the Setup Guide.

IMPORTANT

The Setup Guide explains how to install and test the libm2k library, which handles communciation between the M2K device and the MATALB application on your computer. Once you have verified your programming environment using the Setup Guide, proceed to Section 4.2 of the lab to learn how to write a script using the M2K.m class to interface with the M2K device.

4.2 Procedure

Keep the voltage follower circuit from the previous section.

The following script demonstrates how to:
1. Create a sine wave using the SignalLab class.
2. Generate the sine wave through the DAC (W1) using the M2K class.
3. Read both ADC channels (Ch1 and Ch2) using the M2K class.
4. Plot the input and output signals of the voltage follower.

Step 1: Create the M2K object and enable channels.

myM2K = M2K();                % create M2K object
myM2K.enableAnalogIn(1);      % enable Ch1
myM2K.enableAnalogIn(2);      % enable Ch2
myM2K.enableAnalogOut(1);     % enable W1
myM2K.enablePowerSupply(1);   % enable V+
myM2K.enablePowerSupply(2);   % enable V-

Step 2: Configure the sampling rates and the power supplies.

ADCRate = 1000000;        % ADC rate = 1MHz 
DACRate = 750000;         % DAC rate = 750kHz

% set the ADC and DAC rates
myM2K.setAnalogOutSampleRate(DACRate);
myM2K.setAnalogInSampleRate(ADCRate);

myM2K.setPowerSupply(1, 5);         % set V+ to 5V
myM2K.setPowerSupply(2, -5);        % set V- to -5V

Step 2: Use the SignalLab class to define the sine wave

waveFreq = 1000;      % sine wave frequency (Hz)
amplitude = 1;        % sine wave amplitude (V)

s_generated = SignalLab(amplitude, waveFreq, DACRate);
s_generated.info();
[t_generated, samples_generated] = s_generated.generate(0.01);

Step 3: Generate the sine wave on M2K through W1.

myM2K.setWaveform(1, samples_generated);

Step 4: Acquire samples.

Clear the ADC buffer before reading to avoid stale data.

myM2K.clearAnalogInSampleBuffer();

% acquire 10 complete periods from Ch1 and Ch2
[t_received, ch1_samples, ch2_samples] = ...
myM2K.getAnalogInSamples(10 / waveFreq);

Step 5: Apply a smoothing filter.

Vout_samples  = smoothdata(ch1_samples,  'movmedian', 15);
Vin_samples = smoothdata(ch2_samples, 'movmedian', 15);

Step 6: Plot the results.

figure;
plot(t_received, Vin_samples, "g", "LineWidth", 1.2);  hold on;
plot(t_received, Vout_samples, "r--", "LineWidth", 1.2);
title(sprintf('Voltage Follower Response at %d Hz', waveFreq));
xlabel('Time (s)');
ylabel('Voltage (V)');
legend('Ch2 - Input (V_{in})', 'Ch1 - Output (V_{out})');

MATLAB screenshot showing the input and output waveforms of a unity-gain voltage follower circuit. The main display shows two overlapping sinusoidal waveforms at 1 kHz: a green Channel 2 waveform and a dashed red Channel 1 waveform. The two waveforms are nearly identical in amplitude and phase, confirming that the output follows the input with unity gain and no phase shift.

Figure 6: Expected output of the MATLAB script. Zoom in on the plot to observe the difference between the input and output readings of the voltage follower circuit.

Lab Deliverable #11

Run the script above. Confirm that the output follows the input as expected for a unity-gain voltage follower. Add your name as a second line of the plot title using subtitle() or by modifying the title() call. Upload the figure as an image via the course submission app. Your name must be visible in the image before uploading.

Lab Deliverable #12

List all valid ADC sample rates and all valid DAC sample rates for the M2K hardware, in units of sps (samples per second). Refer to the setAnalogOutSampleRate and setAnalogInSampleRate functions in M2K MATLAB Class — User Guide.

Lab Deliverable #13

Which set of rates determines the sampling frequency of the ADC channels (Ch1 and Ch2)? Which set determines the sampling frequency of the DAC outputs (W1 and W2)?

5. Lab Procedure: Unity-Gain Amplifier as a Buffer

The high input resistance of the op amp (zero input current) means there is very little loading on the generator; i.e., no current is drawn from the source circuit and therefore no voltage drops on any internal resistance. Thus in this configuration the op amp acts like a "buffer" to shield the source from the loading effects from other parts of the system.

From the perspective of the load circuit, the buffer transforms a non-ideal voltage source into a nearly ideal voltage source. Figure 7 describes a simple circuit that we can use to demonstrate this feature of a unity-gain buffer. Here the buffer is inserted between a voltage-divider circuit and some "load" resistance:

Circuit diagram of a unity-gain buffer with a 10 kilohm load resistor. A sinusoidal voltage source connects from ground through two series 4.7 kilohm resistors to ground, forming a voltage divider. The midpoint node between the two resistors is labeled Vin and connects to the non-inverting input pin 3 of op-amp OA. Channel 2 oscilloscope probes Vin to ground. The inverting input pin 2 is connected directly to the output pin 1 via a feedback wire, creating unity-gain voltage follower operation. The output pin 1 connects to node Vout, where Channel 1 oscilloscope probes to ground and a 10 kilohm load resistor connects to ground. The circuit demonstrates that the buffer drives the 10 kilohm load without loading the input voltage divider.

Figure 7: Buffer Circuit #1 with the 10 k$\Omega$ load resistor.

5.1 Hardware Setup

Lab Deliverable #14

Take a clear photograph of your buffer circuit on the breadboard. Make sure the connections are neat. Submit the image via the course submission app. Your name must be visible in the photo.

IMPORTANT

Leave the power supplies off. Get your setup checked off by TA or lab assistant before proceeding to the next step.

5.2 Procedure

Lab Deliverable #15

Screenshot of the oscilloscope display showing $V_{in}$ and $V_{out}$ simultaneously at 1 kHz with the 10 k$\Omega$ load. Submit the image via the course submission app. Your name must be visible in the image before uploading.

Lab Deliverable #16

Record the measured amplitude of $V_{in}$ with the 10 k$\Omega$ load, including units.

Lab Deliverable #17

Record the measured amplitude of $V_{out}$ with the 10 k$\Omega$ load, including units.
- Remove the 10 k$\Omega$ load and substitute a 1 k$\Omega$ resistor instead. (You do not have to turn off the power supply. You only need to turn off the power supplies if there is a major reconstruction.)

Circuit diagram of a unity-gain buffer with a 1 kilohm load resistor. A sinusoidal voltage source connects from ground through two series 4.7 kilohm resistors to ground, forming a voltage divider. The midpoint node between the two resistors is labeled Vin and connects to the non-inverting input pin 3 of op-amp OA. Channel 2 oscilloscope probes Vin to ground. The inverting input pin 2 is connected directly to the output pin 1 via a feedback wire, creating unity-gain voltage follower operation. The output pin 1 connects to node Vout, where Channel 1 oscilloscope probes to ground and a 1 kilohm load resistor connects to ground. Compared to the 10 kilohm load circuit, the heavier 1 kilohm load tests the current-driving capability of the buffer.

Figure 8: Buffer Circuit #2 with the 1 k$\Omega$ load resistor.

Lab Deliverable #18

Record the measured amplitude of $V_{in}$ with the 1 k$\Omega$ load, including units.

Lab Deliverable #19

Record the measured amplitude of $V_{out}$ with the 1 k$\Omega$ load, including units.
- Now move the 1 k$\Omega$ load between pin 3 and ground, so that it is in parallel with the 4.7 k$\Omega$ resistor. Replace the 10 k$\Omega$ load.

Circuit diagram of a unity-gain buffer with a loaded voltage divider input. A sinusoidal voltage source connects from ground through two series 4.7 kilohm resistors to ground, forming a voltage divider. A 1 kilohm resistor is connected in parallel with the lower 4.7 kilohm resistor, significantly loading the divider and reducing the Vin voltage. The midpoint node Vin connects to the non-inverting input pin 3 of op-amp OA and is probed by Channel 1 oscilloscope to ground. The inverting input pin 2 connects directly to the output pin 1 via a feedback wire for unity-gain operation. The output connects to Vout where Channel 2 oscilloscope probes to ground and a 10 kilohm load resistor connects to ground. Comparing this circuit to the unloaded divider version demonstrates how the buffer isolates the output load from the input divider.

Figure 9: Buffer Circuit #3 with the 10 k$\Omega$ load resistor and a 1 k$\Omega$ resistor in parallel with the lower 4.7 k$\Omega$ voltage divider resistor.

Lab Deliverable #20

Record the measured amplitude of $V_{in}$ with the 1 k$\Omega$ resistor in parallel with the lower 4.7 k$\Omega$ voltage-divider resistor. Note how this value has changed compared to Lab Deliverables #16 and #18.

Lab Deliverable #21

Record the measured amplitude of $V_{out}$ for the same configuration (1 k$\Omega$ in parallel with lower 4.7 k$\Omega$), including units.

IMPORTANT

Keep your circuit implementation as is. You will use it again in Lab #7.

Self-Verification Checklist

Before leaving the lab, verify that you have collected all the necessary information to complete your post-lab report:

6. Post-Lab Analysis Report

6.1 Quantitative Analysis

Post-Lab Deliverable #1

Using your measured values of $\Delta V$ (Lab Deliverable #7), $T_r$ (Lab Deliverable #8), and $T_f$ (Lab Deliverable #9), compute the slew rate for both the rising and falling edges using $\text{Slew Rate} = \Delta V / T_r$. Present your results in a table showing: measured $\Delta V$, $T_r$, $T_f$, computed slew rate for both edges, and the LMC662 datasheet specification of 1.1 V/$\mu$s. Work on paper, showing all steps. Photograph your completed work and submit the image via the course submission app. Your name must be visible in the photo.

Post-Lab Deliverable #2

Using your measured amplitudes from Lab Deliverables #16 through #21, and the values you predicted in Prelab Deliverables #6(a), #6(b), and #6(c), construct a comparison table with the following columns: Load configuration, Predicted $V_{in}$ (from prelab), Measured $V_{in}$, Measured $V_{out}$. Work on paper, showing all steps. Photograph your completed work and submit the image via the course submission app. Your name must be visible in the photo.

6.2 Discussion Questions

Post-Lab Deliverable #3

Based on your slew rate measurements in Post-Lab Deliverable #1, discuss any asymmetry between the rising and falling edge results. Suggest a physical reason for the asymmetry, referencing the internal structure of the LMC662 or the nature of the test signal.

Post-Lab Deliverable #4(a)

Using your data from Lab Deliverables #16 through #21, explain how the output amplitude changes with load when no buffer is present between the voltage divider and the load. Reference specific measured values to support your reasoning.

Post-Lab Deliverable #4(b)

Using the same data, explain how the buffer isolates the load from the input voltage divider. Reference specific measured values and compare to your prelab predictions.
You are encouraged to use an AI assistant to help structure your analysis or to clarify concepts such as input and output impedance and the loading effect. Ask it to explain, check your reasoning, or suggest a framework; then apply that framework to your own data. The analysis you submit must be your own work: use AI as a thinking partner, not as a substitute for your own conclusions.

IMPORTANT

Submit your completed work via the course submission app. All plots, images, data tables, and calculations must be clearly labeled and referenced in your post-lab report.

Appendix A: Circuit Construction and Debugging

IMPORTANT

The TA will ask you to describe your wiring color scheme and your initial debugging plan before you power up the circuit in Experiment 1. Be prepared to answer from memory.

A.1 Construction Practices

Neatness directly affects whether your circuit works the first time and how long it takes to find problems when it does not. The following practices are required in this course.

  1. Component placement. Cut and bend resistor and capacitor leads so components lie flat against the board. This keeps the circuit low-profile and stable, and makes pin connections visually verifiable.

  2. Wire length. Use the shortest jumper that reaches between two points. Excess wire length increases parasitic inductance and capacitance; at the frequencies used in Labs 5 and 6 these parasitics are small but not zero. Long wires also create loops that act as antennas and pick up interference.

  3. Color coding. Follow this scheme on every build without exception:

  4. Red: positive supply ($+V_{cc}$, pin 8 of the LMC662)
  5. Black: negative supply ($-V_{cc}$, pin 4 of the LMC662)

  6. Green: ground

  7. Signal flow. Arrange components so the signal path reads left-to-right or top-to-bottom. Place the op-amp in the center of the breadboard with passive components and connections radiating outward from it.

A.2 Debugging Procedure

When the circuit does not behave as expected, resist the assumption that a component has failed. Approximately 99% of circuit problems are wiring errors or power supply issues. Follow this sequence before doing anything else:

  1. Power down immediately. Do not probe a circuit that is behaving unexpectedly while it is energized.

  2. Inspect visually. Check every wire against the schematic. Confirm that each IC pin connects to the correct breadboard row. Confirm the IC orientation (pin 1 at the notch).

  3. Verify power with the M2K voltmeter. Before any signal is applied, confirm that $+V_{cc}$ (pin 8) reads $+5$ V and $-V_{cc}$ (pin 4) reads $-5$ V with respect to ground. A missing supply rail is the single most common cause of op-amp failure in the lab.

  4. Verify ground continuity. Confirm that the M2K GND, the breadboard ground rail, and the op-amp ground reference are all connected.

  5. Check component values. Use the Keysight multimeter to confirm resistor and capacitor values match the schematic before insertion.

  6. Probe the signal path. Apply a known input with the M2K signal generator. Use the oscilloscope to follow the signal from source to each stage output. Stop at the first node where the measurement does not match the expected value; that is where the fault is.

Do not ask the TA to find the fault for you. Describe your debugging sequence and the last node where the measurement matched the prediction. That is the information needed to locate the problem.

Appendix B: The LMC662 Operational Amplifier

Data Sheet: LMC662. Open this before completing the prelab deliverables.

B.1 Package and Pin Assignment

The LMC662 is a dual op-amp: two independent op-amps in a single 8-pin DIP package. The two share power supply pins: pin 8 for $+V_{cc}$ and pin 4 for $-V_{cc}$.

Schematic showing pin connections for both LMC662 op-amps side by side. OA: plus IN A pin 3, minus IN A pin 2, OUT A pin 1, with 0.1 microfarad decoupling capacitors on V-plus pin 8 and V-minus pin 4. OB: plus IN B pin 5, minus IN B pin 6, OUT B pin 7. Both op-amps share supply pins 4 and 8

Figure B.1: LMC662 connection diagram. The $0.1\,\mu$F decoupling
capacitors are required on every build. Because pins 4 and 8 are
shared across both op-amps, one capacitor pair placed adjacent
to the supply pins protects both amplifiers simultaneously..

DIP-8 pin diagram of the LMC662 viewed from above. Notch on left marks pin 1. Counterclockwise numbering: pin 1 OUT A, pin 2 minus IN A, pin 3 plus IN A, pin 4 V-minus, pin 5 plus IN B, pin 6 minus IN B, pin 7 OUT B, pin 8 V-plus,.

Figure B.2: LMC662 physical pin configuration (DIP-8, top view). The notch on the left end of the package identifies pin 1. Pins are numbered counterclockwise.

B.2 Key Specifications

Table B.1: LMC662 specifications referenced in Prelab Deliverables #2 through #4 and #7.
| Parameter | Value | Significance |
|---|---|---|
| Supply voltage range | 4.75 V – 15.5 V | Single-supply or dual-supply operation; powered from M2K ±5 V ($V_S = 10$ V) in this lab, well within the rated range. |
| Gain-bandwidth product | 1.4 MHz | At closed-loop gain $G$, the $-3$ dB bandwidth is $1.4\text{ MHz}/G$. See Deliverable #3(a). |
| Slew rate | 1.1 V/µs | Maximum rate of output voltage change. Determines how fast the output can follow a large step. See Deliverable #4(a). |
| CMRR | 85 dB | Signals identical on both inputs are attenuated by a factor of $10^{85/20} \approx 17{,}783$ relative to a differential signal. |
| PSRR | 85 dB | Power supply fluctuations are attenuated by a factor of $10^{85/20} \approx 17{,}783$ at the output. |
| Quiescent current (per amp) | 375 µA | Total dual-package draw: $2 \times 375\ \mu\text{A} = 750\ \mu\text{A}$. Well within M2K supply limits. |

B.3 Decoupling Capacitors

Every op-amp circuit in this course requires a 0.1 $\mu$F capacitor from the positive supply rail to ground and a second 0.1 $\mu$F capacitor from the negative supply rail to ground, placed as close as possible to pins 8 and 4.

Why they are required. When the op-amp output switches or amplifies a transient, it draws a brief surge of current from the supply. If the supply wiring has any inductance (which it always does), this surge creates a momentary voltage dip on the supply rail. A capacitor placed near the IC absorbs the surge locally, preventing the dip from propagating through the supply and coupling into the input through PSRR. Without decoupling capacitors, op-amp circuits at these frequencies often oscillate or produce distorted outputs that are difficult to explain.

Placement. Insert the capacitors in breadboard rows immediately adjacent to pins 8 and 4. Use one capacitor from pin 8 to the nearest ground rail and one from pin 4 to the nearest ground rail. This is shown in Figure B.1.

B.4 M2K Power Supply Configuration

The ADALM2000 provides two programmable DC supply outputs: $V^+$ (positive rail) and $V^-$ (negative rail), both adjustable from the Scopy power supply panel.

  1. Open Scopy and navigate to the Power Supply tab.
  2. Enable $V^+$ and set it to $+5$ V. Enable $V^-$ and set it to $-5$ V. Enable the output.
  3. Connect the M2K $V^+$ terminal to LMC662 pin 8 rail via a red wire.
  4. Connect the M2K $V^-$ terminal to the LMC662 pin 4 rail via a black wire.
  5. Connect the M2K GND terminal to the breadboard ground rail via a green wire. All circuit grounds (M2K oscilloscope GND, signal generator GND, and the breadboard GND rail) must share this connection.

WARNING

Verify supply voltages with the M2K voltmeter before connecting any signal to the circuit. Confirm $+5$ V at pin 8 and $-5$ V at pin 4 with respect to the ground rail. Do not proceed to Experiment 2 until these readings are confirmed and the TA has checked off your power connections.

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