ECE Emerge Project: Phase 1 -- Signal Conditioning Bring-Up

Department of Electrical and Computer Engineering

Spring 2026

Overview

This lab launches the ECE Emerge capstone project. The complete project description, system architecture, technical requirements, check-off criteria, and deliverables are specified in the ECE Emerge Project Document. Read that document in full before the first lab session.

Phase 1 covers the full analog signal conditioning chain and its first connection to MATLAB. The four hardware stages build and verify the INA125 instrumentation amplifier, the inverting summing amplifier, and the RC low-pass filter with buffer on a solderless breadboard. The fifth stage is a MATLAB demonstration: the team connects the verified breadboard to the M2K, runs an acquisition script adapted from Lab 6, and shows a TA that the complete chain produces the expected voltage swing and noise level as weight changes. After Phase 1, one team member transfers the verified design to a soldered prototype on the M2K adapter board. The breadboard circuit must be fully working — hardware and MATLAB — before any soldering begins.

Lab 8 is different from Labs 1 through 7 in two important ways. First, all work except the Reflective AI Exercise is team work — teams of four students design, build, and report together; three-member teams are permitted when enrollment does not divide evenly into groups of four. Second, teams are not restricted to a single assigned lab section. The five bring-up stages may be completed across any combination of available lab sections during the lab week. A team member can complete a stage in any open section, as long as the result is documented and shared with the rest of the team immediately.

Because no fixed procedure is given, the team's pre-lab design document is the guide. The checkpoints below define the minimum progress required for a satisfactory Phase 1 milestone.

IMPORTANT

Each team member must have completed Lab 7 before the team receives an INA125. The INA125 is a precision integrated circuit. Apply supply voltages carefully. A replacement for a destroyed device may be available subject to a grading penalty.

Individual and Team Work

Individual work. The Reflective AI Exercise (Section 1) is completed independently by each team member before the first lab session. Each member submits their own reflection to Gradescope. Discussing the concepts with teammates is encouraged; the written submission must be each person's own work.

Team work. Everything else — the pre-lab design document, the five bring-up stages, Stage 5 MATLAB demonstration, and the Phase 1 Milestone Report — is a team deliverable. One submission per team.

How team work functions in Lab 8. In Labs 1–7, each student worked independently at their own station and submitted their own results. Lab 8 is structured differently. The team divides the bring-up stages among its members, with each person taking primary responsibility for one or more stages. Primary responsibility means that person leads the task during the lab session, makes sure the measurements are taken and documented, and can explain the results in detail to the team and to the evaluator.

Taking primary responsibility for a stage does not mean the rest of the team is absent or uninvolved. All team members must understand every stage well enough to discuss it, contribute to the milestone report, and answer questions at project check-offs. The evaluator will ask questions of any team member, not only the person who performed the measurement. If one member cannot explain a result that another member produced, that is a team failure, not an individual one.

Using multiple lab sections. The team is not restricted to its own assigned section. Any team member may attend any open lab section during the lab week. A common pattern is for two members to complete Stages 1–2 in one section, then two others (or the same pair) to complete Stages 3–4 in a later section, with all meeting together for Stage 5 and the TA sign-off. Whatever the plan, results and photographs must be shared with the full team in real time — not after the fact.

Coordination plan. The first deliverable in Section 2 is a written team coordination plan submitted with the pre-lab. It specifies who takes primary responsibility for each stage and how the team will keep all members informed. Submitting this plan is required; it is also useful — teams that plan explicitly make fewer coordination errors during bring-up.

1. Individual Pre-Lab: Reflective AI Exercise

Completed individually. Due: Tuesday noon, submitted before entering the lab.

1.1 Reflective AI Exercise: Instrumentation Amplifier and Signal Chain

Objective: Demonstrate understanding of how the INA125 three-op-amp topology solves the limitations of the difference amplifier, and how the Wheatstone bridge and instrumentation amplifier together form a critical complete signal chain from mechanical force to digital value.

Part 1: Exploration

Example prompts are provided below. You may use them, adapt them, or write your own at the same level of specificity.

Focus Area 1: The Three-Op-Amp INA Topology

"I am an electrical engineering student designing an instrumentation amplifier signal chain. Can you explain what goes wrong with a single op-amp difference amplifier when the source impedance is not perfectly balanced between the two input terminals? Describe the effect on common-mode rejection in physical terms."

Follow up with:

"Now explain how the three-op-amp instrumentation amplifier topology solves this problem. Focus on why the input buffer stage is necessary, and how the single shared resistor $R_\text{G}$ controls differential gain without degrading common-mode rejection. Use the virtual short concept to explain what voltage appears across $R_\text{G}$ and why."

Then make it concrete with numbers:

"Using the INA125 gain formula $G = 4 + 60\,\text{k}\Omega / R_g$, calculate the value of $R_g$ needed for a gain of 100. Then apply the virtual short rule: if the differential input to the INA125 is 10 mV, what voltage appears across $R_g$, what current flows through it, and what does the input stage contribute to the overall output? Trace the number through each step."

Focus Area 2: The Wheatstone Bridge as a Signal Source

"I am connecting a Wheatstone bridge load cell to an instrumentation amplifier. Can you explain what the bridge output represents physically, and why both output terminals sit near the same voltage even when a load is applied? Why is this common-mode voltage not a defect to be eliminated before amplification?"

Follow up with:

"The INA125 specifies a CMRR of 90 dB at a gain of 100. The bridge common-mode voltage is approximately 2.5 V. Calculate how much of that common-mode voltage appears at the INA125 output. Then estimate how much would appear at the output of a single op-amp difference amplifier built with 1% tolerance resistors at the same gain of 100. Compare both results to the amplified 10 mV differential signal, and explain why the single op-amp approach is inadequate for this application."

Focus Area 3: Signal Chain to ADC -- From Millivolts to Bits

"A 12-bit ADC with a $\pm 2.5$ V input range has 4096 counts across a 5 V full-scale window. My bridge at full load produces 10 mV of differential output riding on a 2.5 V common-mode. After INA amplification at a gain of 400 on a $\pm 5$ V supply with the reference pin grounded, the INA output spans 0 V at no load to some voltage at full load. Identify the two problems that prevent this signal from using all 12 bits of ADC resolution, and calculate the effective number of bits actually available before any correction."

Follow up with:

"I add an inverting summing amplifier after the INA. The stage must map 0 V INA output to $+2.5$ V at the ADC input, and the full-load INA output to $-2.5$ V. Write the two boundary conditions, solve for the resistor ratios $R_f/R_a$ and $R_f/R_b$ (where $R_b$ connects to the $-5$ V supply rail), and verify the result numerically at both endpoints."

After completing all three focus areas, connect them to your design: the INA125 gain is set by a single external resistor $R_\text{G}$. If you increase the gain by reducing $R_\text{G}$, what constraint does that place on the input signal range, and how does the bridge output level determine where you set that limit?

Part 2: Reflection

Complete the three short-answer responses below. Each is graded independently on its own rubric. Write in complete sentences; bullet lists do not satisfy any of the three responses.

Prelab Deliverable #1a -- The Architecture (60--100 words)

Explain why the three-op-amp INA topology achieves high CMRR when a single op-amp difference amplifier with 1% resistors cannot. Your answer must state what the virtual short forces to happen across $R_g$, and explain why this makes the differential gain of the input stage controllable without changing its common-mode gain.

Prelab Deliverable #1b -- The Numbers (40--75 words)

State the approximate common-mode error voltage at the output of (a) the INA125 and (b) a 1%-resistor single op-amp difference amplifier, for a 2.5 V common-mode input at a gain of 100. Compare each to the amplified 10 mV differential signal. State in one sentence which circuit is adequate for this application and why.

Prelab Deliverable #1c -- The Signal Chain (60--100 words)

Identify the two reasons the INA output alone does not use the full ADC range and calculate the effective number of bits available before correction. Then explain how the summing amplifier corrects both problems in a single stage, and name the specific design constraint (bridge output voltage, INA output swing limit, or ADC input range) that determines each of its two resistor ratios.

2. Team Pre-Lab: Design Document

One submission per team. Due: Tuesday noon, submitted to Gradescope before entering the lab.

2.0 Team Coordination Plan

Submit this plan as the first item of the Team Pre-Lab. It does not require calculations — it requires the team to have a conversation before the lab week begins and to commit that conversation to writing.

Prelab Deliverable #1: Team Coordination Plan

Provide the following in the order listed below.

1. Team roster. List each team member's name and their assigned lab section.

2. Bring-up stage assignments. For each bring-up stage, name the team member taking primary responsibility and the lab section in which that stage will be completed. Every member must be assigned primary responsibility for at least one stage.

2.0 Team Coordination Plan
Stage Primary Lab section planned
Stage 1: INA125 bring-up
Stage 2: Summing amplifier
Stage 3: Load cell and end-to-end
Stage 4: Low-pass filter
Stage 5: MATLAB capture and TA sign-off

3. Report writing assignments. For each section of the Milestone Report, name the team member who will write the first draft.

2.0 Team Coordination Plan
Report section First-draft author
Section 1: Design Decisions
Section 2: Bring-Up Results
Section 3: Discrepancy Analysis
Section 4: Plan for Phase 2

4. Communication plan. In two to three sentences, describe how the team will share measurements, photographs, and circuit notes with members who are not present at a given lab session. The plan must ensure that every member has the information they need to contribute to the milestone report and to answer questions at project check-offs, regardless of which stages they personally performed.

This is the team's engineering design document, not a worksheet. It is the evidence that the team has thought through the system before picking up a component. The signal chain design procedure is worked through in full in Example 11.2 of Chapter 11. The INA125 gain formula is:

$$G = 4 + \frac{60\,\text{k}\Omega}{R_g}.$$

Consult the INA125 datasheet for the pinout, supply limits, and output swing specification.

The total signal chain gain from bridge output to ADC input is the product of the INA gain and the summing amplifier gain: $G_\text{total} = G_\text{INA} \times G_\text{sum}$. The INA is not required to fill its full output swing on its own. Distributing gain across both stages gives more practical component values: concentrating all gain in the INA forces $R_g$ into the single-digit ohm range, where contact resistance and parasitic effects introduce significant error. A practical lower bound is $R_g \geq 30\,\Omega$. The summing amplifier provides both the DC level shift and additional signal gain through its resistor ratio $R_f/R_a$; a larger $R_f/R_a$ reduces the required INA gain and raises $R_g$ to a more reliable value.

Prelab Deliverable #2

INA gain selection.
State the selected INA gain and the summing amplifier signal gain ($R_f/R_a$). Show the calculation of $R_g$ from the INA125 gain formula. Identify the nearest standard resistor value and state the gain it produces. Justify the gain split: the INA gain need not fill the full output swing — choose a value that gives $R_g \geq 30\,\Omega$ to avoid contact-resistance errors, and assign the remaining required gain to the summing amplifier. State the resulting total signal chain gain and verify that the INA output at full load stays within the INA125 output swing limit.

Prelab Deliverable #3

Summing amplifier design.
Derive the resistor ratios $R_f/R_a$ and $R_f/R_b$ from the two boundary conditions (zero load maps to $+2.5$ V; full load maps to $-2.5$ V). Note that $R_f/R_a$ is the signal gain of the summing stage: it is set by how much the INA output swing must be further amplified to fill the full 5 V ADC window, and its value depends directly on the INA gain chosen in Deliverable #2. $R_f/R_b$ sets the DC offset using the $-5$ V rail and is independent of the INA gain. State the specific standard resistor values selected. Write out the complete transfer function $v_\text{ADC} = f(v_\text{INA})$ and verify it numerically at both endpoints.

Prelab Deliverable #4

Theoretical resolution.
Calculate the weight resolution per ADC count (in grams per count) for your chosen gain, the 500 g measurement range, and the M2K 12-bit ADC with a 5 V input range. State how this compares to the 1.1 g jelly bean target.

Prelab Deliverable #5

INA125 pinout diagram.
Provide an annotated diagram of the INA125 pinout (from the datasheet or the project document) showing the intended connection for every pin: positive and negative supply, both differential inputs, both gain pins with $R_g$, the reference pin (IAref, pin 5), and the output. No pin should be left unlabeled.

Prelab Deliverable #6

Low-pass filter design.
The INA125 gain-bandwidth product is approximately 600 kHz. At your chosen INA gain $G_\text{INA}$, the amplifier already limits signal bandwidth to $f_\text{INA} \approx 600\,\text{kHz}\,/\,G_\text{INA}$. Calculate this bandwidth for your design and state why it is still insufficient to reject 60 Hz power-line interference at the ADC input.

Select a cutoff frequency $f_c$ in the range of 2–10 Hz for a passive first-order RC low-pass filter placed after the summing amplifier. Calculate $R$ and $C$ using standard component values available in the lab ($f_c = 1/(2\pi RC)$). Choose $R$ in the range 10 k$\Omega$ to 200 k$\Omega$: large enough to keep $C$ in the range where practical film capacitors are available, but small enough that resistor thermal noise does not corrupt the 12-bit ADC reading. The lab stocks four film capacitor values for this stage. With $R = 100\,\text{k}\Omega$ they give: 820 nF ($f_c \approx 2$ Hz), 470 nF ($f_c \approx 3.4$ Hz), 330 nF ($f_c \approx 5$ Hz), and 150 nF ($f_c \approx 10$ Hz). Pick the value that gives the cutoff your design requires; if your chosen $R$ is not 100 k$\Omega$, scale accordingly.

Use a film capacitor (polyester or Mylar), not ceramic and not electrolytic. Ceramic capacitors exhibit a piezoelectric effect: mechanical vibration or a bump on the table generates a spurious voltage that the ADC reads as a phantom weight change. Electrolytic capacitors have dielectric leakage that acts like a parallel resistor, shifting the cutoff frequency and introducing a DC offset that drifts the zero reading. Both effects directly corrupt a precision scale measurement.

Calculate the attenuation at 60 Hz in dB: $A = -20\log_{10}\!\sqrt{1+(60/f_c)^2}$. Justify your choice of $f_c$: too high leaves 60 Hz interference in the signal; too low increases settling time and slows the scale response.

The RC filter output connects to the remaining op-amp in the dual package, wired as a unity-gain voltage follower. Explain in one sentence why the buffer is necessary between the RC filter and the ADC input. Provide a schematic of the complete filter stage with all component values labeled.

Prelab Deliverable #7

Breadboard plan.
Provide a sketch of the proposed breadboard layout showing the placement of the INA125, the op-amp used for the summing stage, the RC low-pass filter, the op-amp buffer, power connections, decoupling capacitors, and the load cell interface. Stage separation must be clearly indicated.

Blank solderless breadboard with two main terminal strips separated by a center divider channel. Each strip has rows of five electrically connected tie points in columns numbered along the edges. Two power bus strips run along the top and bottom long edges, each with a red positive rail and a blue negative rail separated by a divider. The breadboard provides the layout grid on which the team's component placement sketch should be drawn.

Figure: Blank solderless breadboard. Use this as the layout grid for your breadboard plan sketch.

3. Phase 1 Bring-Up

This is an open-ended engineering session. The team's design document is the guide. Build and verify each stage in isolation before connecting the stages together. Refer to the Analog Circuit Prototyping Best Practices appendix of the project document throughout.

Complete INA125 instrumentation amplifier circuit with load cell interface showing the Wheatstone bridge connected to the differential inputs, gain-setting resistor between pins 8 and 9, decoupling capacitors on the supply pins, reference and sense connections, and the output with a 1 kilohm load resistor to ground.

Figure 1: Complete INA125 instrumentation amplifier circuit with load cell interface. The gain is set by the resistance between pins 8 and 9.

WARNING

Power off the breadboard before modifying any circuit connection. Do not apply power to a stage that has not been checked for wiring errors. Verify supply voltages at the IC pins after every power-on.

3.1 Stage 1: INA125 Bring-Up in Isolation

The circuit that you will implement, on a solderless breadboard, is shown in Figure 1 before connecting the load cell. Make sure your wiring is neat and you use representative colored wires. DO NOT BUILD THE WHOLE CIRCUIT, YOU MUST BUILD IT IN STAGES AS INSTRUCTED BELOW. ALSO, DO NOT CONNECT IT TO THE LOAD CELL AT THIS STAGE. Instead of the load cell, you should use four resistors to produce a predictable test differential voltage input for verifying gain.

  1. Power verification.
    Connect $\pm5$ V to the INA125 supply pins. Tie the load cell ground wire, the M2K analog ground (black wire), and the breadboard ground bus to the same rail — a single shared ground point prevents M2K switching-supply return currents from creating small voltage differences across the signal ground that the ADC would read as phantom weight changes. Before applying any input, power on and measure the supply voltages at the IC pins with the M2K voltmeter.

  2. Balanced bridge test.
    Connect four resistors in the range of 1 k$\Omega$ in a bridge configuration. Choose resistors such that an approximate 10 mV differential signal is produced by the bridge. To start things off, use $R_f$ resistor without the potentiometer (you will later find optimum $R_f$ and add the potentiometer to adjust the total feedback resistance). Choose $R_f$ to produce a gain of 100.

Lab Deliverable #1a

Measure the resistor values accurately and estimate what differential voltage will be produced. If it is not approximately a 10 mV signal with 10 V excitation, place larger resistors in parallel with the bridge resistors. Without connecting the INA125 input pins, measure the differential input voltage from component mismatch in the resistor bridge, and confirm it is in the expected range.

  1. INA output measurement.
    Now, connect the input signal to INA125 input pins, measure output voltage. Calculate the measured gain from your measurements: $G_\text{meas} = V_\text{out} / (V_1 - V_2)$. Compare to the expected set gain. Does the measured value make sense? If not, troubleshoot the circuit.

Lab Deliverable #1b

Take a photograph of the completed Stage 1, and submit.

3.2 Stage 2: Summing Amplifier Bring-Up in Isolation

Test the summing amplifier separately before connecting it to the INA125 output. Use the M2K power supply to provide a DC voltage substituting for the INA output.

  1. Zero-input condition.
    Apply 0 V DC to the summing amplifier input. Measure the output. The designed output at zero input is $+2.5$ V.

Lab Deliverable #2a

Measured output voltage at 0 V input. Percent error from the designed value of $+2.5$ V.

  1. Full-scale input condition.
    Apply the full-scale INA output voltage from your team's design to the summing amplifier input. Measure the output. The designed output at full-scale input is $-2.5$ V.

Lab Deliverable #2b

Measured output voltage at full-scale input. Calculated transfer function slope from the two measurements. Percent error from the designed value of $-2.5$ V. Photograph of the completed Stage 2 breadboard.

3.3 Stage 3: Load Cell Connection and End-to-End Measurement

Connect the load cell to the INA125 inputs only after Stage 1 has been verified and signed off. The load cell wires are color-coded; consult the load cell specifications in the project document Appendix A for the correct wiring assignment.

WARNING

Handle the load cell carefully. Do not apply forces beyond the 500 g maximum design load. Do not bend the cable sharply near the connector.

  1. Polarity verification.
    Place a small weight on the load cell and measure the INA125 output voltage. The output must increase (become more positive) as weight is added. If it decreases, the signal wires are reversed at the INA125 inputs — swap the connections to IN$+$ and IN$-$ and re-verify before proceeding.

Why this matters: the summing amplifier stage is designed for a positive INA output at full load. Reversed signal wires produce a negative INA output, which the inverting summing amplifier drives above $+2.5$ V — saturation, not a correctable slope reversal. Catching this here takes thirty seconds; catching it after Stage 2 is already wired costs much more.

  1. Unloaded baseline.
    With the load cell connected and no weight applied, record the INA125 output voltage and the ADC reading from the M2K.

Lab Deliverable #3a

Measured INA output voltage at zero load. M2K ADC reading at zero load. M2K screenshot.

  1. Known-weight test.
    Place a known calibration weight (use a labeled lab standard, do not estimate) on the load cell. Record the INA125 output voltage and the M2K ADC reading.

Lab Deliverable #3b

Known weight used (state the value in grams). Measured INA output voltage under load. M2K ADC reading under load. Calculated implied sensitivity in mV/g from the two INA output measurements.

  1. End-to-end signal chain.
    Connect the INA125 output to the summing amplifier input. Record the ADC input voltage (summing amplifier output) at zero load and under the known weight. Confirm that zero load maps to approximately $+2.5$ V and that load maps toward $-2.5$ V.

Lab Deliverable #3c

ADC input voltage at zero load and under known weight. Confirmation that signal polarity is as designed (ADC reading decreases as load increases). Photographs of the complete breadboard with load cell connected.

3.4 Stage 4: Low-Pass Filter Bring-Up

This stage verifies the passive RC filter and op-amp buffer added after the summing amplifier. The INA125 at high gain already limits bandwidth to a few hundred Hz, but 60 Hz power-line interference still passes through. The RC filter brings the cutoff frequency down to the 2--10 Hz range selected in Prelab Deliverable #6, and the buffer prevents the ADC input impedance from loading the filter.

Bring up the filter independently before inserting it into the signal chain.

Practical note: decoupling.
Before powering up this stage, verify that a 0.1 µF ceramic capacitor is placed as close as possible to each LMC662 power supply pin. The LMC662 is a CMOS op-amp; without adequate supply decoupling it can oscillate at high frequency, adding broadband noise that appears as random jitter in the weight reading and makes the low-frequency filter behavior impossible to characterize.

  1. Cutoff frequency verification.
    Apply a sine wave from the M2K function generator directly to the RC filter input. Vary the frequency to locate the $-3$ dB point, where the buffer output amplitude equals $0.707\times$ the input amplitude. Compare the measured cutoff frequency to your prelab design value.

Lab Deliverable #4a

Measured $-3$ dB frequency (state how it was determined). Percent error from the prelab design value. M2K screenshot showing input and output waveforms at the measured $-3$ dB point.

  1. 60 Hz rejection.
    Apply a sine wave at exactly 60 Hz to the filter input. Measure the output amplitude at the buffer output. Compute the measured attenuation: $A_\text{meas} = 20\log_{10}(V_\text{out}/V_\text{in})$. Compare to the value calculated in Prelab Deliverable #6.

Lab Deliverable #4b

Input and output amplitudes at 60 Hz. Measured attenuation in dB. Percent error from the prelab calculated value. M2K screenshot.

  1. End-to-end signal chain with filter.
    Insert the complete filter stage into the signal chain: load cell $\to$ INA125 $\to$ summing amplifier $\to$ RC filter $\to$ buffer $\to$ ADC. Record the M2K ADC readings at zero load and under the known calibration weight used in Stage 3.

Lab Deliverable #4c

ADC reading at zero load with filter in the chain. ADC reading under the known calibration weight with filter in the chain. Comparison to the Stage 3 end-to-end readings -- the filter must not shift the DC operating point. Photographs of the complete four-stage breadboard.

3.5 Stage 5: ADC Capture Demonstration

This stage requires a TA sign-off. The TA must witness the demonstration before the team leaves the lab session.

Get this sign-off done before Memorial Day weekend. Stage 5 TA sign-off is the gate that releases the hardware-prototype kit (second INA125, bare prototype board, header connectors). A team that has not been signed off by the start of the long weekend (Saturday, May 23) loses several days of soldered-prototype build time and goes into Check-Off 2 prep already behind. Additional TA sign-off slots will be scheduled for Friday afternoon, May 22 so every team has a clear path to clear this gate before the break; details will be announced separately. Plan your week around hitting this milestone.

With all four signal conditioning stages verified and the complete chain connected, this stage closes the measurement loop to MATLAB. The goal is to confirm that a MATLAB script can acquire the conditioned weight signal, compute a meaningful mean and standard deviation, and display the expected polarity and swing across the weight range. Students completed the necessary M2K-MATLAB skills in Lab 6; the script here is a direct adaptation of that work.

Before opening MATLAB, close Scopy if it is running. The M2K can only communicate with one application at a time. MATLAB will fail to connect to the M2K if Scopy holds the USB link open.

  1. Set up the acquisition. Open your Lab 6 M2K acquisition script in MATLAB. Ch1 should already be connected to the buffer output (the final stage output) from Stage 4. Set the ADC sampling rate to a valid M2K rate in the range of 1 kHz to 100 kHz (the list of valid rates is from Lab 6, Deliverable #12). Add a comment to your script stating the chosen rate and computing the sample count: $N = 0.5 \times f_s$.

  2. Zero-load acquisition. With nothing on the scale pan, run the script. Acquire at least 0.5 seconds of Ch1 samples. Compute and display the mean and standard deviation of the voltage.

  3. Loaded acquisition. Place the calibration weight used in Stage 3 on the pan. Run the script again. Record the mean and standard deviation.

  4. Verify before calling the TA.

  5. Mean voltage must decrease as load increases (negative slope: zero load $\approx +2.5$ V, heavier load lower).
  6. The voltage difference between zero load and the test weight must be at least proportional to the weight fraction of the full scale. For example, a 250 g weight should produce a shift of approximately half the full expected swing.

  7. The standard deviation must be small compared to the signal swing (a well-functioning chain typically shows a standard deviation well below 100 mV at this stage).

  8. Demonstrate for the TA. Call the TA when the criteria above are satisfied. The TA will specify two loads (one of which may be zero). For each load, the team runs the script and displays the mean voltage and standard deviation.

The TA also performs an independent verification of the signal chain, similar in style to the project's Soldered Prototype check-off (Check-Off 2). Using a known weight set (and the lab oscilloscope if helpful), the TA checks:

If the MATLAB acquisition is not yet working but the hardware passes the first three checks, the TA will still release the hardware-prototype kit (second INA125, bare prototype board, header connectors) so that soldered-prototype work is not held up by a stalled script. The MATLAB portion of the sign-off must still be completed for full Lab Deliverable #5 credit and for the Phase 1 Milestone Report; the team returns for that sign-off once the script is running. The point of this carve-out is simple: software bugs are recoverable in the team's own time, but lost soldering time before Memorial Day weekend is not.

Lab Deliverable #5: TA Sign-Off

TA signature confirming the demonstration. For the Phase 1 Milestone Report, include: the selected sampling rate and justification, the sample count $N$, and the mean voltage and standard deviation at each test weight from the MATLAB demonstration. The hardware portion of the sign-off may precede the MATLAB portion; both are required for full credit, but the hardware sign-off alone is sufficient to release the hardware-prototype kit.

4. Phase 1 Milestone Report

One submission per team. Due: Tuesday May 26, noon.

How to submit: Submit the milestone report through the Canvas assignment for Lab 8 Phase 1 Milestone Report. The team's report text (all four sections) and photographs are bundled together in a single submission package; step-by-step submission instructions are on the Canvas assignment page. Name each photograph by stage (e.g., Stage1_Breadboard.jpg, Stage3_LoadCell.jpg, Stage4_Complete.jpg).

The milestone report documents the team's engineering decisions and bring-up results. It is a design record: what the team decided, why, what was measured, and what discrepancies were found.

Before writing a single word, read the Technical Report Requirements and Writing Guide (linked on Canvas under Project Resources). This milestone report is a structured practice run for the full technical report due at the end of the project. The four sections below map directly onto a full engineering report: Design Decisions → Design, Bring-Up Results → Results, Discrepancy Analysis → Discussion, Plan for Phase 2 → Conclusion. The guide explains what belongs in each section, shows weak and strong paragraph examples, and describes the team writing process — including the read-aloud review step that must be completed before submission.

AI Feedback on Your Draft (Advisory — Not a Grade)

When the team submits the milestone report, an AI grader reads each section's text and returns formative feedback. The feedback is advisory — it is intended to help the team identify gaps before the final report at the end of the project. It is not a grade. The milestone report is graded by a human.

The team may resubmit before the deadline as many times as needed. Submit your first draft early — well before Tuesday May 26 — so the team has time to read the AI feedback, discuss it, revise, and resubmit at least once before the hard deadline. A team that submits for the first time on Tuesday morning gets no benefit from the feedback loop and loses the main point of the milestone.

Format. For each section, the AI checks a set of required content elements and style/mechanics (units, figure references, third person, consistent notation, grammar and composition). Each element is returned as one of:

The AI also produces a short section-level summary naming the strongest aspect and the single most impactful revision to make next.

What the AI cannot assess. The AI does not see photographs or M2K screenshots, and it does not know the team's specific chosen design values. It cannot verify whether a gain calculation is numerically correct, whether a proposed cause in Section 3 is physically plausible, or whether a referenced photograph shows the correct circuit. Those checks are flagged for the human grader.

Treat the feedback as guidance, not as an oracle. The AI is good at flagging missing required content, bare values without engineering reasoning, and repeated style problems. It is not a substitute for the team read-aloud step described in the Writing Guide.

Section 1: Design Decisions

Section 2: Bring-Up Results

Section 3: Discrepancy Analysis

Section 4: Plan for Phase 2

Next Step: Soldered Prototype

TA sign-off of Stage 5 (Lab Deliverable #5) is the trigger for the hardware-prototype hand-out. When the TA signs off the Stage 5 ADC capture demonstration, the team is eligible to collect three new items from the teaching staff:

The team performs two soldering tasks on the bare board. First, solder the header connectors into the correct positions, following the same procedure used in Lab 1. Second, solder the four signal-conditioning stages directly onto the prototype area itself, rather than attaching a solderless breadboard on top of the headers as in earlier labs. The second INA125 is soldered into this prototype area and is consumed by the build.

Do not break down the breadboard until the Soldered Prototype passes Check-Off 2 in the project. The breadboard with the first INA125 stays in service as a parallel test platform while the new board is being built and tested, so other team members can continue GUI tuning and calibration work in parallel.

Once Check-Off 2 has passed, the first INA125 must be recovered from the breadboard (insert a small flat-blade screwdriver under one end of the IC and lift it a fraction of a millimetre at a time, alternating ends, taking care not to bend any of the pins) and returned to the teaching staff, who will log the return against the team's equipment record. Failure to return the first INA125 will cost the team credit for the equipment portion of the project.

Refer to Logistics → Equipment Access and Appendix B → Soldered Prototype Phase in the project document for further detail and construction guidance.

Submission Instructions

IMPORTANT

Individual submissions (each team member): Prelab Deliverables 1a, 1b, and 1c (Reflective AI Exercise) -- submitted individually to Gradescope, due Tuesday noon.

Team submissions (one per team): Prelab Deliverables 1--7 (Design Document) -- due Tuesday noon. Phase 1 Milestone Report -- submitted through the Canvas assignment for Lab 8 Phase 1 Milestone Report (report text + photographs bundled in one submission package; see the Canvas assignment page for step-by-step instructions) -- due Tuesday May 26, noon. Submit a first draft well before the deadline so the team can act on AI feedback and resubmit a revised version. All images must be named by stage and all calculations must be clearly labeled within the text.

In-lab sign-off: Lab Deliverable #5 (Stage 5 ADC Capture Demonstration) is signed off by the TA during the lab session. The team must obtain the TA signature before leaving. The Stage 5 results are reported in Section 2 of the Milestone Report.

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