ECE Emerge: Digital Scale Project

Overview

The Jelly Belly factory is transitioning from selling jelly beans by weight to charging per individual bean. This change demands a measurement system capable of resolving a single jelly bean from the total weight on the pan.

Teams consist of four members; three-member teams are permitted when enrollment does not divide evenly into groups of four. Your team will design, build, and demonstrate a high-resolution digital scale that measures weights up to 500 g with sufficient accuracy to detect a single jelly bean. (Note: The average mass of a Jelly Belly bean is approximately 1.10 grams; see Appendix D for relevant statistical background.) The system must operate as a standalone measurement solution: hardware, signal conditioning, analog-to-digital conversion, software, and a user interface are all the team's responsibility.

Unlike the structured lab experiments completed earlier in the course, this project does not specify how to build the system. Chapter 11 of the reader (The Signal in the Difference) and Chapters 10 and 9 provide the theoretical foundation. The team is expected to draw on that material, consult datasheets, and make engineering decisions independently.

Project Objectives

Design and build a digital scale that:

• Weighs objects from 0 to 500 g.
• Achieves a resolution sufficient to detect the addition or removal of a single jelly bean.
• Provides a user-friendly interface for calibration, taring, and weight display.
• Functions as a complete standalone system suitable for practical use.

Scale Performance Criteria

An effective scale design satisfies six performance criteria. Each criterion is defined below and motivates specific design choices described in the sections that follow.

Resolution is the smallest weight change the scale can reliably detect. It is set by how fully the signal conditioning chain uses the 12-bit ADC input window. With a 500 g range, the theoretical limit is $500/4096 \approx 0.12$ g per count. Reaching this limit requires the conditioned signal to span as close as possible to the full $\pm 2.5$ V ADC input range. Every unused volt of ADC range is wasted resolution.

Accuracy is the closeness of the displayed weight to the true weight. It cannot be achieved from nominal component specifications alone. Tolerances, load cell sensitivity variation, and amplifier offsets produce systematic errors that differ from unit to unit. Accuracy is established through calibration against known reference weights and maintained through a tare function that zeros out the container weight before measurement.

Linearity is the consistency of sensitivity across the full 0–500 g range. It requires that no stage in the signal chain saturates or clips at any point in the measurement range. The load cell itself contributes less than 0.03% non-linearity at full scale; signal chain saturation from incorrect gain selection is the dominant risk.

Settling time is how quickly the reading stabilizes after a weight is placed. It is governed primarily by the low-pass filter cutoff frequency. A lower cutoff frequency rejects more 60 Hz interference but slows the response. At a cutoff of 5 Hz, the filter settles to within 2% of its final value in approximately 120 ms, which is adequate for a practical weighing application.

Zero stability is the constancy of the unloaded reading over time. It is affected by thermal drift in the load cell (rated at 0.3% of full scale per 10°C) and by warm-up drift in the electronics during the first 30 minutes of operation. It is managed by allowing at least 30 minutes of warm-up before calibration and by providing a tare reset in the software.

Noise floor is the minimum signal distinguishable from random variation. It is dominated in this system by 60 Hz power-line interference coupled into the load cell wiring and breadboard. It is mitigated by twisted-pair wiring, single-point grounding, the anti-alias low-pass filter, and software averaging of multiple ADC readings.

These six criteria are not independent. Resolution and settling time trade against each other through the filter cutoff frequency: a lower cutoff improves noise rejection but slows response. Accuracy and linearity both require that the signal chain cover the full measurement range without saturation. The system architecture and technical requirements in the sections that follow are chosen to satisfy all six criteria simultaneously within the constraints of the available hardware.

System Architecture

The scale consists of five subsystems. The team is responsible for the design and integration of all five.

Figure 1: System overview: five subsystems from sensor to user interface.

1. Sensing Element. A Wheatstone-bridge load cell converts an applied weight into a small differential voltage. In this design, the load cell is used to measure weights in the range of 0–500 grams. Note that the specific load cell provided is capable of measuring up to 5 kg, but its full dynamic range will not be utilized here. See Appendix A for the load cell specifications.

2. Signal Conditioning. Three stages process the millivolt-level bridge output before it reaches the ADC. The INA125 instrumentation amplifier (first stage) amplifies the differential bridge signal; it must be powered from the $\pm 5$ V split supply on the M2K adapter board. The team designs the second stage, a summing amplifier, which applies an inverting gain and a DC offset derived from the $-5$ V rail to map the full measurement range to the full ADC window. The third stage is a passive RC anti-alias low-pass filter followed by a unity-gain buffer, which attenuates 60 Hz power-line interference and band-limits the signal before digitization. Relevant theory is covered in Section 11.4 of the reader.

3. Data Acquisition. The M2K analog-to-digital converter (ADC) digitizes the conditioned signal. The M2K communicates with MATLAB over USB.

4. Computer Interface. MATLAB code configures the M2K ADC and acquires data. See the course website for the USB interface reference.

5. Graphical User Interface. A MATLAB App Designer GUI provides calibration, taring, and weight display.

Figure 2: The load cell platform used in this project.

Technical Requirements

This section specifies what the system must do. Supporting material lives in the appendices: load cell specifications and the distinction between component range and design range (Appendix A, especially A.0); construction practice for the breadboard and soldered prototype (Appendix B); wiring practice and other noise mitigation (Appendix C); the statistical quantities used in the GUI display (Appendix D); and the calibration procedure (Appendix E).

Prototype Platform

The system must be implemented on a soldered M2K adapter board prototype (Appendix B). The solderless breadboard is the bring-up platform for Lab 8 only; it is not a permitted final platform for the calibration, performance characterization, or final demonstration phases of this project.

Why this is a requirement. Calibration constants are only meaningful on a circuit that does not change between sessions. Jumper wires on the solderless breadboard shift between sessions and develop intermittent contacts, and unshielded load cell wiring picks up significant noise. The GUI's calibrated state and tare offset are only useful if the underlying hardware reading is stable. A robust, soldered prototype is the foundation that every subsequent step (multi-point calibration, noise characterization, jelly-bean detection verification, the final demonstration) depends on.

Equipment timeline. The hardware-prototype kit (the bare prototype board, its header connectors, and a second INA125) is issued by the teaching staff at TA sign-off of Lab 8 Stage 5 (Lab Deliverable #5). The first INA125 stays on the breadboard until Check-Off 2 passes, then is carefully recovered and formally returned to the teaching staff. See Logistics → Equipment Access for the full procedure, including the screwdriver-based recovery of the first INA125 and the requirement that the return be logged.

Convert early: this is front-loaded work. As soon as the breadboard is verified end-to-end in Lab 8, transition immediately to the soldered prototype. Do not defer this conversion to start calibration, GUI polish, or report drafting first. Teams that defer soldering consistently lose bring-up time later, debugging a flaky breadboard while trying to take calibration data; front-loading this work makes the rest of the project markedly easier and protects the team against late-project hardware failures that cannot be recovered from in time for the final demonstration.

Potentiometer budget. The final soldered prototype shall include at most two potentiometers. Use fixed resistors for every other gain and offset value in the signal chain. A prototype loaded with adjustable trimmers is harder to characterize, harder to reproduce, and tempts the team into tuning the system to a single calibration session rather than committing to a documented, repeatable design.

Signal Conditioning Requirements

• ADC utilization. The M2K ADC has a 12-bit resolution and an input range of $-2.5$ V to $+2.5$ V (5 V total). The signal conditioning chain must be designed so that the full 500 g measurement range, the design range (Appendix A.0), corresponds to as close to the full 5 V ADC input range as is achievable. Signal conditioning that uses only a fraction of the ADC range wastes resolution proportionally. Section 11.4 of the reader quantifies how unused ADC range degrades effective resolution.

• Theoretical resolution. With a 5 V ADC range and 12-bit conversion, the ADC partitions the input into 4,096 levels of approximately 1.2 mV each. At 500 g full scale, this corresponds to a theoretical weight resolution of:

$$\frac{500\,\text{g}}{4096} \approx 0.12\,\text{g per level}.$$

The objective is to approach this limit as closely as practical constraints allow.

• Supply configuration. The INA125 must be powered from the $\pm 5$ V split supply on the M2K adapter board, with the reference pin (IAref, pin 5) connected to ground. The summing amplifier second stage uses the $-5$ V rail to generate the DC offset required to shift the signal to the lower ADC boundary at zero load.

• Signal polarity. The ADC reading decreases as load increases: zero load produces approximately $+2.5$ V at the ADC input and full load produces approximately $-2.5$ V. This negative slope results from two factors acting together: the inverting topology of the summing amplifier, and the orientation of the load cell signal wires at the INA125 inputs. Both matter. The summing amplifier is designed for a positive INA output at full load; it inverts that positive swing to reach $-2.5$ V at the ADC. If the load cell signal wires are reversed (IN$+$ and IN$-$ swapped at the INA125), the INA output goes negative with increasing load; the inverting summing amplifier then drives the ADC input above $+2.5$ V, causing saturation rather than a correctable slope reversal. Verify INA output polarity immediately after connecting the load cell: the INA output must increase (become more positive) as weight is added. If it decreases, swap the two signal wires at the INA125 inputs before proceeding. The calibration software must account for the negative slope when converting ADC readings to weight.

• Linearity. No amplifier stage shall saturate and the ADC input shall not clip at any point across the full 0–500 g measurement range. The conditioned signal must map the full weight range monotonically to within the $\pm 2.5$ V ADC window. Saturation at either end of the range is the most common signal chain failure mode and produces a hard limit on effective measurement range that calibration cannot correct.

• Anti-alias low-pass filter. A passive first-order RC low-pass filter followed by a unity-gain op-amp buffer must be placed between the summing amplifier output and the ADC input. The cutoff frequency must be in the range of 2–10 Hz, providing a minimum of 15 dB attenuation at 60 Hz. The buffer is required to prevent the ADC input impedance from loading the filter and shifting the cutoff frequency.

• Noise. The dominant noise source in this system is 60 Hz power-line interference. The combined effect of the anti-alias filter, twisted-pair load cell wiring, single-point grounding, and software averaging must reduce measurement noise to below one ADC count at the displayed output. See Appendix C for required wiring and grounding practices.

Sampling Rate Selection

The M2K ADC supports a set of discrete sampling rates (you listed these in Lab 6, Deliverable #12). Choosing the right rate for this application requires balancing three considerations.

Anti-aliasing. The RC low-pass filter limits the conditioned signal to at most $f_c$ Hz before it reaches the ADC. The Nyquist criterion requires the ADC sampling rate to exceed $2 f_c$. With a 10 Hz filter cutoff, any rate above 20 sps satisfies anti-aliasing; every valid M2K rate exceeds this by orders of magnitude. The filter is doing its job; aliasing is not the binding constraint here.

Statistical averaging. Each displayed weight reading is computed from a 0.5-second window of samples. The number of samples in that window is $N = 0.5 \times f_s$. A well-estimated mean and standard deviation require $N$ to be reasonably large. The standard error of the mean decreases as $1/\sqrt{N}$, so doubling the sample count improves the estimate by $\sqrt{2}$ (see Appendix D for the underlying statistical definitions). Practical targets:

USB throughput and memory. At 1 MHz, each 0.5-second acquisition transfers 500,000 double-precision values (4 MB). This is not a problem for a single acquisition, but it sets an upper limit on how quickly the display can update. At 10 kHz, the same window transfers 5,000 values and completes in well under a millisecond of processing time. There is no benefit to running the ADC faster than the application requires.

Design recommendation. For this scale, a sampling rate in the range of 1 kHz to 100 kHz is appropriate. Choose the valid M2K rate in this range that you prefer, document the choice, and compute the sample count $N = 0.5 \times f_s$ in your code. Report $N$ alongside every displayed reading so the evaluator can verify your averaging window. Using 1 MHz (as in the Lab 6 script) is acceptable but unnecessary; if you retain it, explain why in your design decisions.

GUI Requirements

The graphical user interface must support the following functions.

1. Interface design. Intuitive layout with clearly labeled controls, status indicators for calibration and tare state, and real-time display updates.

2. Calibration. A multi-point calibration routine using a minimum of five reference weight standards distributed across the 0–500 g range (Appendix E describes the procedure and how to create your own calibrated standards). The user enters the known mass of each standard; the GUI records the corresponding ADC voltage, displays a live calibration plot (ADC voltage versus known weight) that updates as each point is added, and computes a linear least-squares fit. The $R^2$ coefficient of the fit must be displayed so the user can assess calibration quality before accepting it. Calibration parameters (slope and intercept) are stored and applied automatically to all subsequent weight readings. The GUI must indicate persistently whether the scale is in a calibrated state.

3. Taring. A tare control that resets the displayed weight to zero, adjusts live readings to exclude the tared weight, and maintains the tare state until explicitly reset.

4. Output display. Each displayed weight reading is computed as the mean of at least 0.5 seconds of consecutive ADC samples. The display shows the mean weight in grams, the standard deviation of the sample set, and a 95% confidence interval on the mean (see Appendix D for definitions). A jelly bean count estimate is derived from the calibrated mean weight using the reference mean bean mass of 1.10 g; the display shows weight and estimated count simultaneously and updates continuously as new sample windows complete.

5. Software averaging. All weight readings displayed to the user must be based on a minimum of 0.5 seconds of ADC samples. Individual raw ADC readings must not be displayed as weight values. The sample count used for each reading must be reported alongside the measurement.

Project Roles

Every team member contributes to every part of the system, every check-off, and every section of the report. Within that shared responsibility, each member also takes on one of four complementary specialist roles. The role is about ownership and expertise, not exclusion. The role holder is the team's designated integrator and point of contact for that area, and the person who goes deepest in it.

A three-member team distributes the fourth role across the other three (see Role 4 below).

Role 1: Analog Hardware & Signal Chain

Owns the team's signal conditioning electronics, the path from the load cell to the ADC input. This includes:

• Load cell wiring and signal-polarity verification (Lab 8, Stage 3).
• INA125 instrumentation amplifier stage: gain selection, $R_g$, $\pm 5$ V supply configuration.
• Summing amplifier stage: gain ratios, inversion, $-5$ V offset.
• Anti-alias RC low-pass filter and unity-gain buffer.
• Breadboard layout, transition to the soldered M2K adapter board prototype, and debugging when any stage does not look right.

Lead author of Section 1 of the final report (Technical System Design and Implementation). Lead at Check-Off 2 (Soldered Prototype).

Role 2: M2K–MATLAB Interface & GUI

Owns the team's software stack, from the M2K driver layer up to the App Designer user interface. This includes:

• libm2k installation and verification on the team's machines (Lab 6, Section 4.1).
• Use of the M2K and SignalLab classes to configure the M2K, choose an ADC sample rate appropriate for the application (see Sampling Rate Selection above), manage the analog input buffer, and acquire samples. The MATLAB control pattern was introduced in Lab 6 Section 4.2; the project extends it.
• App Designer GUI: calibration workflow with live plot and $R^2$ display, tare control, real-time output display (mean, standard deviation, 95% CI, sample count $N$, bean count), and a clearly visible state model (uncalibrated / calibrated; un-tared / tared).
• A timer-driven acquisition loop that keeps the GUI responsive while continuous 0.5-second sample windows stream in.

This role applies, at project scale, the M2K–MATLAB interface introduced in Lab 6. Where Lab 6 acquired ten periods of a 1 kHz sine wave on demand, the project acquires continuous 0.5-second windows of the conditioned load-cell signal and displays the running mean and statistics live.

Lead author of Section 3 of the final report (MATLAB GUI Development and User Experience). Lead at Check-Off 1 (GUI Prototype).

Role 3: Calibration & Performance Analysis

Owns the team's measurement quality, the procedures and analysis that turn working hardware and software into a calibrated scale. This includes:

• Creating the team's calibrated weight standards from available objects using the lab reference scale (Appendix E.2).
• Designing and executing the multi-point calibration procedure: at least five reference weights distributed across 0–500 g, linear least-squares fit, $R^2$ check, mid-point verification.
• Characterising the scale against the six performance criteria (resolution, accuracy, linearity, settling time, zero stability, noise floor).
• Statistical analysis: mean, standard deviation, variance, 95% confidence intervals, outlier detection (Appendix D).
• Identifying the dominant error source and explaining how it was diagnosed.
• Verifying that the system can reliably detect a single jelly bean given the measured noise floor.

Lead author of Section 2 of the final report (Calibration and Performance Analysis). Lead presenter at the Final Demonstration: drives the calibration and measurement on the evaluator's selected load cell.

Role 4: System Integration & Technical Report (4-member teams)

Owns end-to-end integration and the coherence of the team's deliverables. This includes:

• Coordinating the hardware-software handoff: the moment the signal-conditioning output reaches the M2K ADC and the MATLAB code starts seeing real data.
• Project timeline and task tracking: who is doing what, when blockers form, what is on the critical path to each check-off.
• Submitting the report sections through the course's sectioned submission system: managing the AI-feedback rounds per section (see Appendix F), incorporating feedback, tracking which sections are at which stage.
• Editing the report for coherence: enforcing consistent terminology and notation across sections; eliminating contradictions between Section 1 (what was built), Section 2 (how it performs), and Section 3 (how it is operated).
• Convening team meetings and keeping everyone informed of project status (Logistics → Project Timeline).

Lead author of Sections 4 and 5 of the final report (Team Collaboration and Project Management; Problem-Solving and Learning Outcomes).

Three-member teams distribute this work as follows: the Calibration & Performance lead absorbs the integration responsibilities (they are already the natural bridge between hardware and software); Section 4 of the report is led by the Hardware lead, Section 5 by the Calibration lead, with the GUI lead reviewing for consistency.

Guardrails (read these as you choose roles)

• Ownership, not exclusion. The role holder is responsible for the area, but every team member contributes to every part of the project.
• Every team member reads every file. No part of the codebase, schematic, or report is "off-limits" to a non-owner. The role holder is the integrator, not a gatekeeper.
• All members must be present at the Final Demonstration. The evaluator may select any team member to present.
• The individual exit survey asks each member to describe their personal contributions specifically. General statements such as "we all participated equally" will not be credited.

Role Declaration

Each team declares its role assignments through one submission per team, due:

Friday, May 22 at 12:00 PM (noon).

The submission process will be announced separately. Until then, use the time to read the role descriptions above with your teammates, discuss which roles suit each member's interests and strengths, and reach agreement before the declaration window opens.

Project Check-Offs

Two graded check-offs are scheduled, followed by a final demonstration. At each check-off, different team members are expected to lead the demonstration. Evaluators note which team members are present and engaged across all check-offs.

Lab 8 serves as the breadboard bring-up and ADC capture milestone. The four signal conditioning stages (INA125, summing amplifier, RC low-pass filter, and unity-gain buffer) are verified individually, end-to-end, and with MATLAB acquisition as Lab 8 deliverables, including a TA-witnessed ADC capture demonstration (Lab 8, Stage 5). The M2K-MATLAB interface is established in Lab 6. The two project check-offs build on these completed foundations.

Check-Off 1: GUI Prototype

15 minutes. At least one team member must be present.

This check-off verifies the MATLAB App Designer GUI with the actual signal conditioning hardware. Simulation using the DAC is not acceptable at this stage.

Bring to the check-off:

• The working signal conditioning breadboard (verified in Lab 8) with load cell attached.
• A functioning App Designer GUI.

The GUI must demonstrate at minimum:

• Calibration: Collect at least five reference weight standards across the 0–500 g range. The live calibration plot updates as each point is added. The $R^2$ coefficient is displayed. After accepting calibration, the GUI indicates calibrated state and applies the stored slope and intercept to all subsequent readings.
• Taring: A tare control that zeros the display and maintains the tare offset until reset.
• Output display: Mean weight in grams, standard deviation, and 95% confidence interval, updated continuously using 0.5-second sample windows.

The evaluator will place known weights on the scale and verify that the displayed value agrees with the known weight to within the expected accuracy of the calibrated system.

Check-Off 2: Soldered Prototype

15 minutes. At least one team member must be present.

This check-off verifies that the signal conditioning circuit has been successfully transferred from breadboard to the soldered prototype area on the M2K adapter board.

Bring to the check-off:

• All four signal conditioning stages soldered on the M2K adapter board prototype area, with load cell attached.

The evaluator will perform a hardware test of the signal chain, from the Wheatstone bridge through to the ADC clock (see Figure 1). Your M2K will be connected via USB to a MATLAB script, which will carry out automated testing of your hardware implementation. Voltage outputs will be measured at 0 g, 250 g, and 500 g loads. The expected response is approximately +2.5 V at zero load, decreasing to about −2.5 V at full load. Statistical data will be collected for each load condition.

Final Project Demonstration

Each team has a 15-minute slot. All team members must be present. Thirty minutes before the demonstration, teams may set up and calibrate using a specified load cell. The evaluator will select one team member to present on behalf of the group.

The team must:

• Estimate the number of jelly beans in a closed container. A similar empty container will be provided for taring.

• The evaluator will place tell you to perform a measurement of a unloaded cell, a 250 gram weight (will be provided by the evaluator), and 500 gram weight (wll weight will be provided by the evaluator). your GUI ashould show a plot of weight versus ADC output voltage demonstrating that the design achieves close to a 5 V swing without saturating any amplifier stage with approximately $+2.5$ V at zero load decreasing to approximately $-2.5$ V at full load.

• The evaluator will repeat the same hardware test as in Check-off #2 (this test does not use your GUI)

Deliverables and Grading

Final Report

A concise technical report, prepared by the team, documenting the system implementation, emphasizing design decisions made and their rationale, and providing suggestions for improvement based on observations during testing and calibration. See Appendix F for the report prompts.

Individual Exit Survey

Each team member must complete an individual exit project survey. The survey asks each member to describe their personal contributions to the project and to evaluate the contributions of each teammate. General statements such as "we all participated equally" are not acceptable and will not be credited.

Logistics

Team Composition

Teams consist of four members. A three-member team is permitted when enrollment does not divide evenly into groups of four. Each team member takes one of the four complementary specialist roles described in Project Roles above; three-member teams distribute the fourth role across the other three as specified there. All team members share responsibility for design, construction, and reporting. The individual exit survey (see Deliverables) requires each member to document their personal contributions.

Lab and Support Schedule

After Lab 7, no further lab sessions are scheduled. To facilitate project work:

• Teams may attend any lab section to work on the project or seek assistance from teaching assistants.
• Instructor and teaching assistant office hours remain available for technical questions.

Project Timeline

• Regular team meetings are essential. All members must be informed of project status and task assignments at all times.
• Front-load the conversion from breadboard to soldered prototype; see Technical Requirements → Prototype Platform for the requirement and the rationale.
• Clear Lab 8 Stage 5 TA sign-off before Memorial Day weekend. Stage 5 sign-off is the gate that releases the hardware-prototype kit (second INA125, bare prototype board, header connectors); a team that misses this gate before the long weekend loses several days of soldered-prototype build time and goes into Check-Off 2 prep already behind. Additional TA sign-off slots will be scheduled for Friday afternoon, May 22 so every team has a clear path to clear this gate before the break; details will be announced separately.

Equipment Access

• A reference electronic scale is available in the lab. Teams use it to create their own calibrated weight standards from available objects (see Appendix E).
• INA125 instrumentation amplifiers (two per team) and the bare prototype board. Each team is issued two INA125 chips over the course of the project. The two units have very different roles:
  • First INA125 is issued once at least one team member has completed Lab 7. This unit is used on the solderless breadboard for Lab 8 and Check-Off 1. It is a returnable unit: it must be handed back to the teaching staff at the end of the project (recovery procedure below).
  • The hardware-prototype kit (second INA125, bare prototype board, and the header connectors that go on it) is issued together at TA sign-off of Lab 8 Stage 5 (Lab Deliverable #5: the TA-witnessed end-to-end ADC capture on the breadboard). The bare prototype board is the platform for the soldered prototype, and the team is responsible for two soldering tasks on it. First, solder the header connectors into the correct positions, following the same procedure used in Lab 1. Second, solder the four signal-conditioning stages directly onto the prototype area itself (rather than attaching a solderless breadboard on top of the headers as in earlier labs). The second INA125 is soldered into this prototype area and is consumed by the build; it is not expected to be returned in working condition.
  • Do not break down the solderless implementation until the Soldered Prototype has passed Check-Off 2. The breadboard with the first INA125 remains a useful parallel test platform while the soldered prototype is under construction, so other team members can continue GUI tuning, calibration practice, and characterization in parallel while the hardware lead solders and brings up the new board.
  • Recovering and returning the first INA125. Once the soldered prototype is verified at Check-Off 2, carefully insert a small flat-blade screwdriver under one end of the IC on the breadboard and lift it out by prying up a fraction of a millimetre at a time, alternating ends, taking care not to bend any of the pins. Hand the recovered IC to a teaching staff member, who will check it off the team's equipment record. The return must be logged. A team that does not formally return the first INA125 will not receive credit for the equipment portion of the project.
  • (The INA125 is a precision integrated circuit. Apply supply voltages carefully. If a device is destroyed during the project, a replacement may be available subject to a grading penalty.)

Load Cell Checkout

During a lab period, each team may check out a load cell from a teaching assistant or undergraduate lab assistant. One team member must sign the checkout log, recording their name, team number, the date, and the unit’s tag number. At the end of the lab, the load cell must be returned and checked back in by the teaching staff.

A limited number of load cells are available for 48-hour (workday) checkout to support work outside the lab. This requires a separate checkout and check-in process with the teaching staff. Inspect the load cell before leaving the lab and document any pre-existing conditions in the log.

You will be explicitly informed of the required return time. Failure to return the unit by the deadline will result in a point penalty.

Transport and storage. The load cell must be transported and stored in the provided protective enclosure. Do not carry it loose in a bag or backpack. Keep the enclosure upright; do not stack heavy items on top of it. Keep the load cell dry.

Handling. Apply forces only along the primary measurement axis — vertically, through the pan mounting point. Side loads, twisting, and impacts can permanently shift the zero output or crack the strain gauge bond, producing a unit that reads incorrectly even though it looks undamaged. Do not apply loads greater than 500 g during experiments. Do not attempt to disassemble the unit or touch the strain gauge area at the center of the beam.

Cable care. Do not bend, kink, or sharply fold the cable, especially near the connector. Cable damage at the strain relief is the most common failure mode on checked-out units and produces intermittent, noisy readings that are very difficult to distinguish from a circuit problem.

Returning. Return the load cell within 48 hours so other teams can use it. The number of units is limited; a late return may block another team's work.

Reporting damage. If the load cell is dropped, the cable is kinked, or readings behave unexpectedly — zero that drifts continuously, output that does not return to baseline after removing a weight, or an erratic signal at rest — report it to course staff or a TA immediately. Do not return a damaged unit without reporting it. A load cell that appears functional but is out of calibration will corrupt another team's results, and that is a more serious outcome than the original damage. Damage happens; concealing it is the problem.

Appendix A: Load Cell Specifications

A.0 Component Range vs. Design Range

The load cell used in this project is rated for 5 kg full-scale, but the scale you are building measures 0–500 g. The wider sensor range is not a mismatch; it is a deliberate choice. Smaller commodity load cells in this form factor are not readily available, and the 5 kg unit provides mechanical headroom against accidental overload.

The trade-off is that only the lower 10% of the sensor's full output is used. The signal arriving at the INA125 input is correspondingly small, and the amplifier chain has to make up the difference: it must provide all of the gain needed to map the 0–500 g signal into the ADC's $\pm 2.5$ V window. This places more responsibility on the INA125 and summing amplifier design than would be the case if the sensor were sized exactly to the application.

Keep two ideas separate as you read the specifications below:

• Component range is what the sensor can physically handle as a piece of hardware (the numbers in this appendix).
• Design range is the portion of that range the system is engineered to use (0–500 g for this project).

The two are not the same thing. The specifications below describe the component; the requirements elsewhere in this document describe the design. Confusing the two is a common source of design errors in the amplifier chain.

A.1 General Specifications

F.S. denotes full scale.

For the 5 kg full-scale load cell used in this project, key absolute limits are: non-linearity, creep, and repeatability each at 1.5 g; drift at 2.5 g/3 min; zero temperature drift at 15 g/$10^\circ$C.

A.2 Practical Implications

• Warm-up time. Allow at least 30 minutes of powered operation before calibration and measurement.

• Repeatability. Repeated measurements of the same weight may differ by up to 1.5 g. Statistical averaging improves effective resolution.

• Creep. For measurements extending over time, readings may drift by up to 1.5 g under a constant load.

• Temperature. Changes in ambient temperature affect the zero reading. Maintain a stable environment or account for temperature variation.

• Mounting. Forces must be applied along the primary measurement axis to avoid quadrature error.

Figure A.1: Load cell dimensions.

Appendix B: Analog Circuit Prototyping Best Practices

Analog circuits require a more methodical construction approach than digital circuits. Analog signals are not bounded to fixed voltage levels, and integrated circuit pins do not have built-in reverse polarity protection. The following practices reduce the risk of component damage and wasted debugging time.

Solderless Breadboard Phase

1. Study the pinout before placing any component. Sketch the connections on paper. Check the datasheet pin diagram against your sketch before applying power.

2. Connect power and ground first. Add decoupling capacitors as close as possible to the power supply pins of each integrated circuit. Verify positive and negative supply connections before powering on. After power-up, confirm that current draw is within the expected range.

3. Build and test each stage separately. Verify the instrumentation amplifier stage in isolation before connecting the summing amplifier. Connect the stages only after each has been checked off independently.

4. Test with a known differential input before connecting the load cell. Four 1 k$\Omega$ resistors arranged as a balanced bridge with 2.5 V excitation will produce a small differential voltage due to component tolerances. This provides a safe, predictable test input to verify gain before the load cell is attached.

Soldered Prototype Phase

1. Understand the adapter board layout. Note which pads on the front and back are electrically connected. Vias provide physical through-holes but do not create automatic front-to-back connections; connections must be made deliberately with solder bridges.

2. Place all components on the front of the board. Route all wire connections on the back. Use labels on the back to track pin assignments.

3. Solder every wire to a pad, not into a via. Make each electrical connection by soldering the wire end to a pad on one side of the board. The vias on the prototype area are unplated through-holes and do not, by themselves, complete a circuit; a wire pushed through a via without a solder bond to the pad has no reliable electrical contact and will produce intermittent readings that look like a circuit fault.

4. Match the wire type to the connection. Solid-core wire is appropriate for short, fixed connections between components on the board. For connections that will flex in service, such as between the load cell and the PCB, use multicore (stranded) wire; the strands flex without transmitting stress to the solder joints, while solid-core wire on a flexing connection will eventually crack the joint or the wire. Tin the wire ends with a thin layer of solder before insertion.

5. Solder ICs with minimal solder on each pin to allow desoldering if a component must be replaced.

6. Follow the same stage-by-stage testing sequence as the solderless phase. A soldered circuit that has never been tested in stages is significantly harder to debug.

Figure B.1: Top of the M2K adapter board, with components mounted on the front side.

Figure B.2: Back of the M2K adapter board: wire routing and decoupling capacitor placement. Keep decoupling-capacitor leads short and place each capacitor as close as possible to the IC power pin it decouples.

Figure B.3: Side view of the M2K adapter board showing component height above the board.

Figure B.4: Front of a completed soldered prototype. All four signal-conditioning stages are mounted on the top side of the board.

Figure B.5: Back of the same prototype. Wires are routed on the bottom side and connections are formed by solder bridges between adjacent pads.

Critical Warnings

• Do not power on a complete, untested analog circuit expecting it to function immediately.
• Do not apply power while building or modifying the circuit.
• Do not use a soldering iron on a powered circuit.

Appendix C: Noise Reduction

The bridge output is a differential voltage in the millivolt range. At this signal level, electromagnetic interference (EMI) from power lines, motors, and other sources can be significant relative to the signal of interest. Twisted-pair wiring on the load cell connections is the primary EMI mitigation; software averaging of ADC samples further reduces random noise at the displayed reading.

Twisted Pair Wiring

Twisting the load cell wires together significantly reduces EMI pickup. Each half-twist reverses the orientation of the wire loop, so induced voltages from external fields alternate in direction and cancel when the signal is subtracted differentially. The effectiveness of the cancellation increases with the number of twists per unit length.

Twisted pair wiring is mandatory for all connections to the load cell in the final prototype (Figure 2).

Figure C.1: EMI cancellation by twisted pair wiring. In configuration (a), parallel wires act as antennas and accumulate interference. In configuration (b), alternating twist orientations cause induced voltages to cancel.

Figure C.2: Twisted-pair wiring in practice. Each of the four load cell wires runs between the board and the load cell as part of a single twisted bundle.

Software Averaging

Apply averaging of multiple ADC readings in software; each displayed reading is the mean of at least 0.5 s of samples (see GUI Requirements). If averaging alone is insufficient for a given prototype, a simple digital low-pass filter applied to the sample stream is an alternative.

Appendix D: Statistical Background

Scale performance cannot be evaluated from a single measurement. Multiple repeated measurements of the same weight reveal the distribution of readings around the true value. The following statistical quantities are the minimum required for a rigorous performance characterization. MATLAB provides built-in functions for all of them.

Measures of Central Tendency and Dispersion

Mean. The arithmetic average of the measurements. Estimates the systematic reading for a given load.

Standard deviation. A measure of measurement-to-measurement variability. A lower standard deviation indicates better precision (repeatability).

Variance. The square of the standard deviation. Useful in further statistical calculations.

Coefficient of variation. Standard deviation expressed as a percentage of the mean. Values below 10% generally indicate acceptable consistency for a measurement system.

Confidence Intervals

A 95% confidence interval provides a range within which the true mean lies with 95% probability, given the observed sample. The interval width depends on both the standard deviation and the number of samples. Larger sample counts narrow the interval and improve confidence in the estimated mean.

In the context of this project, a confidence interval on the scale reading for a known calibration weight shows whether the scale has a statistically significant bias. If zero does not lie within the confidence interval, a systematic offset is present.

Outliers

Individual readings that fall far from the majority of measurements may indicate transient noise, mechanical disturbance, or software errors. The interquartile range (IQR) method provides a robust criterion: readings below $Q_1 - 1.5 \times \text{IQR}$ or above $Q_3 + 1.5 \times \text{IQR}$ are flagged as outliers, where $Q_1$ and $Q_3$ are the 25th and 75th percentiles respectively.

Jelly Bean Weight Statistics

A reference sample of 91 jelly beans was weighed individually. Key statistics: mean 1.106 g, median 1.110 g, standard deviation 0.088 g, range 0.45 g. The coefficient of variation is 7.9%, indicating good bean-to-bean consistency within the sample. The natural variability of individual bean weights (standard deviation of 0.088 g) sets a practical floor on counting precision that is independent of scale resolution.

Appendix E: Calibration and Taring

E.1 What Calibration Is and Why It Is Necessary

Calibration establishes the quantitative relationship between the ADC reading and the actual weight on the scale. Without calibration, ADC readings are arbitrary numbers. The relationship must be determined experimentally because component tolerances, load cell sensitivity variation, and amplifier offsets make it impossible to compute the correct conversion factor purely from nominal specifications. Two scales built from nominally identical components will have different calibration constants.

Calibration answers the question: "What weight corresponds to this ADC reading?" It is not a one-time factory setting. It should be repeated whenever the circuit is changed, the load cell is remounted, or the supply voltage shifts significantly.

E.2 Creating Your Own Calibrated Standards

The lab does not have enough certified weights for every team. Instead, one reference electronic scale is available in the lab. Your team uses it to create a set of calibrated standards: ordinary objects whose weight has been accurately measured and recorded. These standards serve as your reference weights throughout the design, bring-up, and testing phases.

Procedure for creating calibrated standards:

1. Collect 6–8 small, dense, stable objects that span the 0–500 g range. Good choices: coins, metal nuts or bolts, small bags of sand or rice tied closed, sealed water bottles. Avoid food items that dry out, liquids in open containers, or anything that compresses or deforms.

2. Weigh each object individually on the lab reference scale. Record the reading to the nearest 0.1 g.

3. Label each object clearly and permanently. A small piece of tape with a written mass works; a luggage tag is better. The label must survive a few weeks of lab use.

4. Store all standards together in a labeled zip-lock bag that stays with your team throughout the project.

5. Choose standards that are well distributed across the range; for example, approximately 50 g, 100 g, 150 g, 200 g, 300 g, 400 g, and 500 g. A cluster of standards near zero and a gap near full scale produces a poor calibration.

6. Before the final demonstration, re-verify two or three of your standards on the reference scale to confirm they have not changed.

Important: Your calibrated standards are only as good as the reference scale reading at the time of weighing. Take the reference reading carefully: place the object gently at the center of the pan, wait for the reading to stabilize, and record the displayed value. Take two readings and average them if the display fluctuates.

E.3 What Taring Is

Taring sets the current scale reading to zero, so that subsequent readings show only the weight added after the tare was applied. It is named after the "tare weight", the weight of the container or packaging that is not part of the measurement of interest.

Example: The evaluator hands the team a closed container of jelly beans and an identical empty container. The team places the empty container on the scale pan and presses the Tare button. The display reads 0.000 g. The team then replaces the empty container with the full one. The display now shows the weight of the jelly beans only, with the container weight automatically excluded.

Taring does not remove the container from the scale. It stores the current reading as an offset and subtracts it from every subsequent reading in software:

$$W_\text{display} = W_\text{measured} - W_\text{tare}.$$

The tare offset must persist in software until the user explicitly resets it. Pressing Tare with nothing on the scale (or with the container already removed) produces a wrong tare value and corrupts all subsequent readings; the GUI should make the workflow unambiguous.

Taring is not calibration. Calibration determines the slope and intercept of the weight-to-ADC conversion. Taring applies a zero-offset after calibration. The correct sequence is always: calibrate first, then tare.

E.4 Two-Point Calibration

The simplest calibration assumes a linear relationship between weight $W$ and ADC voltage $V$:

$$W = m \cdot V + b.$$

Two measurements establish slope $m$ and intercept $b$: one at zero load ($V_0$, $W = 0$) and one at a known reference weight ($V_1$, $W_1$):

$$m = \frac{W_1}{V_1 - V_0}, \qquad b = -m \cdot V_0.$$

Because the summing amplifier is inverting, the ADC voltage decreases as load increases. The slope $m$ will therefore be negative. This is expected and does not indicate a wiring error.

Two-point calibration is accurate at the two calibration points and interpolates between them. Non-linearity in the load cell or amplifier chain degrades accuracy at intermediate points.

E.5 Multi-Point Calibration (Recommended)

Measuring at several known weights distributed across the full 0 to 500 g range and fitting a line by least squares provides a better estimate of slope and intercept. Specific advantages:

• Random measurement noise in individual readings is averaged out across all calibration points.
• The quality of the linear assumption can be assessed from the residual errors and the $R^2$ coefficient.
• Non-linear behavior, if present, becomes visible in the residuals and can be addressed with a higher-order polynomial fit.

A linear fit to calibrated standards distributed across the full range provides substantially better accuracy than a two-point calibration and is the required approach for the final demonstration.

E.6 Practical Calibration Procedure

Follow this sequence each time the scale is calibrated.

1. Warm up. Power on the circuit and allow at least 30 minutes before beginning calibration. Load cell output drifts during warm-up; calibrating on a cold system produces a shifted zero that changes as the circuit reaches thermal equilibrium.

2. Verify supply voltages. Confirm that $+5$ V and $-5$ V are present at the INA125 supply pins before applying any load.

3. Zero-load baseline. With nothing on the scale pan, record the ADC reading ($V_0$). This is the unloaded reference. Record at least 10 consecutive readings and take the mean.

4. Place standards in sequence. Place each calibrated standard on the pan one at a time, from lightest to heaviest. For each standard, wait for the reading to stabilize (approximately 3–5 seconds), record at least 10 readings, and take the mean.

5. Fit the calibration line. In MATLAB, use polyfit(V, W, 1) with the voltage readings as $V$ and the known weights as $W$. Store the returned slope and intercept. Inspect the fit: plot the calibration data and the fitted line on the same axes and verify that no point deviates by more than 2–3 g from the line. A poor fit indicates a measurement error, a mislabeled standard, or non-linearity in the signal chain.

6. Verify at a midpoint. Place a standard that was not used in the calibration fit. The displayed weight should agree with the labeled value within the expected resolution. If it does not, check for a mislabeled standard or a non-linearity in the signal chain.

7. Apply tare only after calibration is complete. Do not tare before or during calibration.

E.7 Calibration in the GUI

The calibration routine must be integrated into the GUI so that it can be repeated without modifying code. The GUI should:

• Guide the user through placing each standard in sequence with on-screen prompts
• Accept the known mass of each standard as a text input or from a pre-loaded list
• Display a live calibration plot (ADC voltage vs. known weight) as points are added, updating with each measurement
• Compute and store the calibration slope and intercept automatically
• Display the $R^2$ value of the fit so the user can assess calibration quality
• Apply the stored calibration to all subsequent weight readings
• Include a clearly labeled Tare button that stores the current calibrated reading as the tare offset and resets the display to zero
• Show the active tare value and provide a Reset Tare button

Appendix F: Final Project Report

Submission Process

The final report is submitted through the course submission system via Canvas. Submit one section at a time: after submitting a section, the system returns AI-generated feedback identifying missing elements, unsupported claims, or unclear reasoning within that section. You may resubmit a section at most twice to receive AI feedback; use those submissions deliberately. Read the feedback carefully and revise thoroughly before resubmitting.

AI feedback is formative only. It flags gaps and weaknesses; it does not grade your work and it cannot assess whether your technical reasoning is correct or your analysis is sound. The final report is evaluated by a human grader. A clean AI feedback response is not a guarantee of a high grade.

All team members must have read and agreed to the content before submission. One submission per team.

Format

Five sections, each approximately one page; treat this as a guide, not a hard limit. Submit each section under its heading. Upload figures, calibration plots, and photographs as separate image files in the same assignment; name each file by section (e.g., S1_Prototype_Front.jpg, S2_CalibrationPlot.png, S3_GUI_Screenshot.png).

Section 1: Technical System Design and Implementation

What to include:

• INA gain selection. State the gain chosen, the $R_g$ calculated, and the nearest standard resistor value used. Explain why gain was split between the INA and the summing amplifier, not just that it was, but what would have gone wrong without the split.
• Summing amplifier design. State the $R_f/R_a$ and $R_f/R_b$ ratios and the standard resistor values selected. Write the transfer function and verify it numerically at zero load and full load.
• Low-pass filter. State the cutoff frequency, $R$ and $C$ values, and calculated 60 Hz attenuation in dB. Explain in one sentence why the unity-gain buffer is required after the RC network.
• Hardware photographs. Completed breadboard with all four stages visible and labeled by stage, and front and back of the soldered prototype.
• Design trade-offs. Identify one decision where competing constraints had to be balanced and explain the reasoning.

What a strong submission looks like. The numbers are present and correct, but reasoning is what distinguishes it. "We chose $R_g = 120\,\Omega$ because it gives $G_\text{INA} = 504$ and keeps contact resistance below 1% of $R_g$" is strong; "We chose $R_g = 120\,\Omega$ to get a gain of approximately 500" is weak, giving a result without the engineering reasoning. Photographs show a neat, clearly staged circuit where individual components and ICs are identifiable.

Section 2: Calibration and Performance Analysis

What to include:

• Calibration procedure. Number of calibration points used, what weights, and how they were distributed across the 0–500 g range. State whether standards were re-verified on the lab reference scale before the final demonstration.
• Calibration results. The calibration plot (ADC voltage vs. known weight) with the linear fit overlaid. Slope, intercept, and $R^2$ of the fit.
• Resolution and accuracy. Weight resolution per ADC count derived from the calibration slope, compared to the theoretical limit of 0.12 g/count. Explain any gap between achieved and theoretical resolution.
• Precision. Standard deviation of repeated readings at two or more test weights. 95% confidence interval on the mean at each.
• Error sources. Identify the dominant source of measurement error in the system and explain how you know it was dominant.

What a strong submission looks like. The calibration plot is included as a figure, not just described. The analysis connects measured performance to design choices: if resolution fell short of 0.12 g/count, the report identifies specifically why (unused ADC range, noise floor, resistor tolerance) rather than noting the gap without explanation. The report states clearly whether the system can reliably detect a single jelly bean (≈ 1.1 g) given the measured noise floor.

Section 3: MATLAB GUI Development and User Experience

What to include:

• Calibration workflow. How the multi-point calibration routine is implemented in App Designer: how the user enters each reference weight, how the live calibration plot updates as points are added, where $R^2$ is displayed, and how calibration parameters are stored and applied to subsequent readings.
• Tare implementation. How the tare offset is stored and applied, and how the GUI makes the tare state visible to the user.
• Real-time display. How the 0.5-second acquisition window is implemented; what is displayed (mean weight, standard deviation, 95% CI, sample count $N$, jelly bean estimate); how frequently the display updates.
• Screenshots. GUI during calibration and during live measurement, with real data visible, not placeholders.
• Challenges. One significant implementation challenge and how it was resolved.

What a strong submission looks like. The description of the calibration workflow is specific enough that a reader could reproduce it: not "the user enters weights and the GUI fits a line" but a description of the actual controls, prompts, and sequence. The report explains design choices, not just features: why the display was organized as it was, what update rate was chosen and why.

Section 4: Team Collaboration and Project Management

What to include:

• Division of responsibilities. Who took primary responsibility for which bring-up stages and which parts of the software and report. Be specific; statements such as "we all contributed equally" will not be credited.
• Cross-section coordination. How the team shared measurements, photographs, and circuit notes when members worked in different lab sections.
• One challenge, resolved. One specific coordination or interpersonal challenge and how it was handled.
• Retrospective. One thing the team would do differently if starting the project again, and why.

What a strong submission looks like. It is specific and honest. It names individuals and their contributions. A team that divided work unevenly but recognized and corrected it mid-project demonstrates more maturity than one that claims perfect balance. The challenge described is real and the resolution explained, not glossed over.

Section 5: Problem-Solving and Learning Outcomes

What to include:

• One significant technical challenge. The most difficult technical problem encountered: not a list, but one specific problem described in enough detail that a reader understands what was observed, what was tried, and how it was resolved.
• Diagnostic process. How the root cause was identified: what measurements were taken, what hypotheses were ruled out.
• Individual learning. Each team member states in one or two sentences what they personally learned that they did not know before. These must be individual statements, not a single team-level reflection.
• Connection to future work. Two to three sentences connecting what the team built to a real engineering application beyond this course.

What a strong submission looks like. The technical challenge is described with specificity: not "we had noise problems" but "we observed 180 mV peak-to-peak noise at the summing amplifier output at rest, which we traced to absent decoupling capacitors on the LMC662 supply pins; adding 0.1 µF ceramic capacitors reduced the noise to under 20 mV." Individual learning statements are genuinely individual; different team members learned different things.