Chapter 11: The Signal in the Difference

The op-amp circuits in Chapter 10 share a common characteristic: each amplifier processes a single voltage measured relative to a common ground. Many real-world sensors do not produce a single-ended output of this kind. A strain gauge changes its resistance when a force is applied. A thermocouple produces a small voltage between two metallic junctions at different temperatures. A bridge sensor for a digital scale generates a small differential voltage, a few millivolts, riding on a much larger common-mode voltage that appears equally on both output terminals.

Amplifying such signals accurately requires an amplifier designed specifically for this purpose. This chapter develops the instrumentation amplifier from first principles, beginning with the simpler difference amplifier, introducing the Wheatstone bridge as the canonical transducer interface, and then showing how the three-op-amp topology resolves the limitations of the single op-amp approach. The chapter concludes with a practical framework for connecting a sensor, an instrumentation amplifier, and an analog-to-digital converter into a complete signal chain.

The Difference Amplifier

The most direct way to amplify a voltage difference is to add a single op-amp with four resistors so that it subtracts one input from the other and scales the result.

Figure: Single op-amp difference amplifier. Resistors $R_1$ and $R_2$ set the inverting-path gain; $R_3$ and $R_4$ set the voltage at the non-inverting input. When the four resistors are matched, the circuit amplifies only the voltage difference $v_2 - v_1$.

Analysis by Superposition

The output of a linear circuit with two independent inputs can be found by analyzing each input separately and summing the results.

Step 1: Set $v_1 = 0$. With $v_1$ replaced by a short to ground, $R_1$ connects the inverting input to ground. The non-inverting input sees the voltage divider formed by $R_3$ and $R_4$:

$$v_+ = v_2 \cdot \frac{R_4}{R_3 + R_4}.$$

The circuit is a non-inverting amplifier with feedback through $R_1$ and $R_2$. Its output due to $v_2$ alone is:

$$v_{\text{out},2} = v_+ \left(1 + \frac{R_2}{R_1}\right) = v_2 \cdot \frac{R_4}{R_3 + R_4} \cdot \frac{R_1 + R_2}{R_1}.$$

Step 2: Set $v_2 = 0$. With $v_2 = 0$, the non-inverting input is connected to ground through $R_3$ in series with $R_4$, giving $v_+ = 0$. The circuit is an inverting amplifier with input $v_1$ through $R_1$ and feedback through $R_2$:

$$v_{\text{out},1} = -\frac{R_2}{R_1} v_1.$$

Step 3: Superpose. The total output is:

$$v_{\text{out}} = v_{\text{out},1} + v_{\text{out},2} = -\frac{R_2}{R_1} v_1 + \frac{R_4}{R_3 + R_4} \cdot \frac{R_1 + R_2}{R_1} \cdot v_2.$$

Matched Resistors

Setting $R_1 = R_3$ and $R_2 = R_4$ simplifies the general expression. The factor multiplying $v_2$ becomes:

$$\frac{R_2}{R_1 + R_2} \cdot \frac{R_1 + R_2}{R_1} = \frac{R_2}{R_1}.$$

The output reduces to:

$$v_{\text{out}} = \frac{R_2}{R_1}(v_2 - v_1).$$

The gain is $R_2/R_1$ and the circuit amplifies only the differential component $v_2 - v_1$. Any voltage common to both inputs (the common-mode voltage) cancels exactly. Setting all four resistors equal gives a unity-gain difference amplifier: $v_{\text{out}} = v_2 - v_1$.

Two Practical Limitations

Although the single op-amp difference amplifier is straightforward to build, it has two limitations that matter in precision applications.

Limitation 1: Finite input impedance. The non-inverting input loads $v_2$ through $R_3 + R_4$. The inverting input loads $v_1$ through $R_1$. When the source driving $v_1$ or $v_2$ has a non-zero output impedance, this loading changes the effective input voltage and therefore the gain. For sensors with source impedances of several kilohms, the resulting error can be significant.

Limitation 2: Sensitivity to resistor mismatch. The cancellation is exact only when $R_1/R_2 = R_3/R_4$ precisely. Physical resistors have tolerances, and any mismatch allows common-mode voltage to appear at the output. Achieving a common-mode rejection ratio (CMRR) greater than 60 dB with discrete resistors requires matched components or a dedicated matched-resistor network.

These two limitations motivate the three-op-amp instrumentation amplifier.

The Wheatstone Bridge

Many physical quantities, including force, pressure, and temperature, are most naturally sensed as a change in resistance. A strain gauge is a resistive element whose resistance increases when it is mechanically stretched. A thermistor changes resistance with temperature. The Wheatstone bridge is the standard circuit for converting a resistance change into a measurable voltage difference.

The bridge consists of four resistors arranged in a diamond between a reference voltage $V_\text{ref}$ and ground. When all four arms respond to the measurand (two increasing by $\delta R$ and two decreasing by $\delta R$ in the opposing pattern shown below), the configuration is called a full bridge. The load cell used in this project is a full-bridge device: four strain gauges are bonded to the beam, two on the top surface and two on the bottom, so that bending places two gauges in tension and two in compression simultaneously.

Figure: Full-bridge Wheatstone bridge circuit consisting of two parallel voltage dividers. All four arms are active: opposing arms change by $+\delta R$ and $-\delta R$ when a load is applied. The measured quantity is the differential output $V_1 - V_2$, which is proportional to $\delta R$.

Figure: Full-bridge Type I load cell. Two strain gauges on the top surface are placed in tension under load ($+\delta R$); two on the bottom surface are placed in compression ($-\delta R$). This opposing arrangement realizes the full-bridge configuration in a single mechanical assembly, and simultaneously rejects axial strain and temperature-induced drift.

The circuit can be analyzed as two voltage dividers connected in parallel between $V_\text{ref}$ and ground. The left divider has a top resistor $R_1 - \delta R$ and a bottom resistor $R_1 + \delta R$, giving midpoint voltage:

$$V_1 = V_\text{ref} \cdot \frac{R_1 + \delta R}{2R_1}.$$

The right divider has a top resistor $R_1 + \delta R$ and a bottom resistor $R_1 - \delta R$, giving:

$$V_2 = V_\text{ref} \cdot \frac{R_1 - \delta R}{2R_1}.$$

The differential output is:

$$V_1 - V_2 = V_\text{ref} \cdot \frac{(R_1 + \delta R) - (R_1 - \delta R)}{2R_1} = V_\text{ref} \cdot \frac{2\,\delta R}{2R_1},$$

which simplifies exactly to:

$$V_1 - V_2 = V_\text{ref} \cdot \frac{\delta R}{R_1}.$$

The full-bridge arrangement produces this result because all four arms contribute: when two arms increase and two arms decrease, the differential outputs of the two dividers add rather than cancel. A configuration with only one active element and three fixed resistors (a quarter bridge) produces half this output for the same $\delta R$, because only one divider changes while the other remains fixed.

Example 11.1: Bridge Output Voltage

A load cell uses a full Wheatstone bridge with nominal resistance $R_1 = 1\,\text{k}\Omega$ and supply $V_\text{ref} = 5\,\text{V}$. When the rated load is applied, each active element changes by $\delta R = 2\,\Omega$. Find the differential output voltage.

Solution. Using the bridge output equation:

$$V_1 - V_2 = 5 \cdot \frac{2}{1000} = 10\,\text{mV}.$$

The bridge converts the full rated load into a differential signal of only 10 mV. Both $V_1$ and $V_2$ sit near 2.5 V; the common-mode voltage is $V_\text{ref}/2$. An amplifier with high CMRR and a gain of at least 330 is required to bring this signal to the full 3.3 V range of a downstream ADC.

Physical Interpretation

The small output voltage in Example 11.1 illustrates a fundamental challenge in sensor interfacing. A typical 12-bit ADC operating from 0 to 3.3 V has a resolution of $3.3\,\text{V}/2^{12} \approx 0.8\,\text{mV}$ per count. A 5 mV signal spans only about six counts out of 4096, which gives an effective resolution of less than three bits. Amplifying the differential signal to span most of the ADC range before digitizing is not optional; it is a design requirement.

Two properties of the instrumentation amplifier are essential in this context. First, the differential gain must be large, on the order of 100 to 1000, to amplify the millivolt bridge output to the volt-level range of the ADC. Second, the CMRR must be high, typically greater than 80 dB, so that the 2.5 V common-mode voltage at the bridge output does not saturate the amplifier or corrupt the measurement.

The Instrumentation Amplifier

Instrumentation amplifiers are high-performance differential amplifiers with high input impedance, precise gain, and high common-mode rejection ratio (CMRR). They are particularly well-suited for amplifying low-level signals from sensors in noisy environments.

The configuration below places two buffer amplifiers before the differential stage. Each buffer has its own gain resistor $R_g$ connected to ground, providing high input impedance.

Figure: Instrumentation amplifier. Each input op-amp has a dedicated gain resistor $R_g$ to ground.

The overall output is:

$$V_\text{out} = \left(1 + \frac{2R_1}{R_g}\right)\left(\frac{R_3}{R_2}\right)(V_2 - V_1).$$

The integrated circuit realization uses an improved topology in which a single resistor $R_g$ connects the two inverting inputs directly, rather than each to ground separately. This arrangement increases the differential-mode gain of the buffer pair while leaving the common-mode gain of the input stage equal to unity, improving CMRR. Applying the Golden Rules to the input stage, the voltage across $R_g$ equals $V_2 - V_1$ exactly, because the virtual short forces each inverting input to follow its respective non-inverting input. The current through $R_g$ flows through both $R_1$ resistors, so the differential output of the input stage is:

$$V_2' - V_1' = \left(1 + \frac{2R_1}{R_g}\right)(V_2 - V_1).$$

The output difference amplifier then applies a gain of $R_3/R_2$, giving the overall result:

$$V_\text{out} = \left(1 + \frac{2R_1}{R_g}\right)\left(\frac{R_3}{R_2}\right)(V_2 - V_1).$$

Figure: Improved instrumentation amplifier. A single resistor $R_g$ connects the two inverting inputs. The differential-mode gain of the input stage is $1 + 2R_1/R_g$; the common-mode gain is unity.

The gain is adjusted by changing $R_g$ alone. The resistors $R_1$, $R_2$, and $R_3$ are fixed and matched; in an integrated circuit they are laser-trimmed for precision. Changing $R_g$ varies the differential gain without disturbing the resistor ratios that govern the CMRR of the output stage.

Figure: Schematic symbol of an instrumentation amplifier IC. The gain-setting resistor $R_g$ connects to two dedicated external pins. Power supply and reference pins are also shown.

Integrated Circuit Realization: INA125

The INA125 is a precision instrumentation amplifier in a single package. Its gain is set by a single external resistor $R_g$ connected between the two dedicated gain pins:

$$G = 4 + \frac{60\,\text{k}\Omega}{R_g}.$$

In any design, the data sheet for the specific device must be consulted. Gain formulas, pin assignments, supply voltage limits, bandwidth, and offset specifications vary across manufacturers and device families. The output swing of the INA125 on a single supply is approximately 1.5 V to 4 V. To bring the signal to a full 5 V range for the M2K 12-bit ADC, the INA125 output is followed by a summing amplifier, which scales the signal and adds a DC offset to fully utilize the ADC input range.

Gain, Bandwidth, and Anti-Aliasing

Every op-amp has a finite gain-bandwidth product (GBW): as the closed-loop gain increases, the usable bandwidth decreases proportionally. For the INA125 the GBW is approximately 600 kHz. At a gain of $G = 330$, the $-3\,\text{dB}$ bandwidth is:

$$f_{-3\,\text{dB}} = \frac{\text{GBW}}{G} \approx \frac{600\,\text{kHz}}{330} \approx 1.8\,\text{kHz}.$$

At the higher gains used in this application (up to $G \approx 6000$), the bandwidth narrows to approximately 100 Hz. The INA therefore acts as a low-pass filter whose cutoff frequency is determined automatically by the gain.

A filter placed before the ADC to remove signal content above half the sampling rate is called an anti-aliasing filter, and the Nyquist criterion explains why such filtering is required. For a digital scale, the signals of interest are slow mechanical phenomena with bandwidths well below 10 Hz. At the gains required to amplify the bridge output, the gain-limited bandwidth of the INA125 is already several decades above the signal band. The INA therefore serves as both the signal amplifier and the anti-aliasing filter simultaneously, provided a sufficiently high sampling rate is used.

In general, a designer should choose the lowest sampling rate that meets the requirements of the application, since this reduces the computational load on the processing unit. The performance of an ADC can be improved through a technique called oversampling, but this topic is beyond the scope of this reader.

Is an anti-aliasing filter needed for an application? Before finalizing any design, verify two conditions: first, that the signal bandwidth of interest lies within $f_{-3\,\text{dB}}$ so the INA does not attenuate the signal of interest; and second, that $f_{-3\,\text{dB}}$ is below the Nyquist frequency of the ADC so that out-of-band noise is rejected before sampling. When both conditions hold, adding a discrete anti-aliasing filter will not improve performance.

Optimizing the Signal Chain

The instrumentation amplifier solves the two core problems of bridge sensor interfacing: it provides high differential gain and rejects the common-mode voltage. However, amplifying the signal is only half the problem. For the measurement to be useful, the amplified signal must also be compatible with the input range of the analog-to-digital converter that digitizes it, and it must contain no frequency content that the converter cannot represent. This section identifies what can go wrong at the analog-to-digital interface and develops a systematic approach to resolving it.

Figure: Complete bridge-based measurement system. The load cell produces a small differential voltage that is amplified by the instrumentation amplifier, level-shifted and scaled by a summing amplifier, band-limited by an anti-alias low-pass filter, then digitized by the ADC and read by the host computer. The role of the anti-alias filter is developed in the subsection below.

ADC Resolution and Dynamic Range

An $N$-bit analog-to-digital converter maps a continuous input voltage over a full-scale range to one of $2^N$ discrete integer codes. The size of one step, called the least significant bit (LSB), is:

$$\Delta = \frac{V_{\text{FS}}}{2^N}.$$

The key principle is: the signal should span the full input range of the ADC. If the signal occupies only a fraction $f$ of the full scale, the effective number of distinguishable levels is $f \cdot 2^N$ instead of $2^N$, and the effective resolution is:

$$N_{\text{eff}} = N + \log_2 f.$$

Since $f \leq 1$, $\log_2 f \leq 0$: bits are lost whenever the signal does not span the full range.

Two Sources of Wasted Range

In bridge-based systems two distinct problems cause the INA output to fall short of the full ADC range, even after amplification.

Problem 1: Amplitude mismatch. The INA output may not span the full $V_{\text{FS}}$. For example, a bridge output of 10 mV amplified by $G = 125$ gives 1.25 V, which uses only 25% of a 5 V ADC range. The effective resolution is $12 + \log_2(0.25) = 10$ bits. Two bits are wasted. The solution is to choose a higher gain, limited only by the output swing of the INA and the available supply voltage.

Problem 2: DC offset. On the split $\pm 5\,\text{V}$ supply used in this application, the INA125 reference pin is tied to ground and the output at zero load is approximately 0 V, which sits at the midpoint of the ADC range. As load increases, the output rises into the positive half of the ADC window only. The negative half is never used, and one full bit of resolution is wasted regardless of the gain chosen.

Both problems are visible in the figure below. Correcting them requires a second amplifier stage that shifts the INA output so that zero load corresponds to one boundary of the ADC range and full load reaches the other boundary. A summing amplifier is well suited to this role: it can apply a gain and add a fixed DC offset simultaneously using a single op-amp stage.

Figure: Output voltage versus applied weight on a split $\pm 5\,\text{V}$ supply. The blue shaded band is the M2K ADC input range ($-2.5\,\text{V}$ to $+2.5\,\text{V}$). Without level shifting (red), the INA125 output spans only the positive half of the ADC range; the lower half is permanently unused. The inverting summing amplifier (green) applies both a gain and a DC offset, mapping zero load to $+2.5\,\text{V}$ and full load to $-2.5\,\text{V}$. The complete 5 V ADC window is utilized.

Example 11.2: Signal Chain Design for the Digital Scale

A digital scale uses a full Wheatstone bridge load cell with nominal resistance $R_1 = 1\,\text{k}\Omega$, rated at 5 kg full scale with a sensitivity of 1.0 mV/V, excited by $V_\text{ref} = 5\,\text{V}$. The design measurement range is 0 to 500 g. At the 500 g full-scale load, the bridge differential output is $v_d = 0.5\,\text{mV}$. The INA125 is powered from $\pm 5\,\text{V}$ with its reference pin (IAref) tied to ground. The M2K ADC has $N = 12$ bits and input range $[-2.5\,\text{V},\, +2.5\,\text{V}]$. Design the INA gain and summing amplifier to fully utilize the ADC range.

Step 1: Choose the INA gain. The load cell is rated 5 kg full scale at 1.0 mV/V with a 5 V reference, giving a full-scale bridge output of $1.0\,\text{mV/V} \times 5\,\text{V} = 5\,\text{mV}$ at 5 kg. The design range is 500 g, which is 10% of rated full scale, so the bridge output at full design load is $5\,\text{mV} \times 0.10 = 0.5\,\text{mV}$. With the reference pin at ground, the INA output at zero load is approximately 0 V and rises with increasing load.

On a $\pm 5\,\text{V}$ supply the INA125 output swing is approximately $\pm 4\,\text{V}$. A tempting first move is to put all of the required gain in the INA and drive its output right up to this limit at full design load:

$$G_\text{max} = \frac{4\,\text{V}}{0.5\,\text{mV}} = 8000.$$

This is the upper bound set by the output swing, not a recommended design point. At $G = 8000$ the gain-setting resistor is:

$$R_g = \frac{60\,\text{k}\Omega}{8000 - 4} \approx 7.5\,\Omega,$$

which is too small to build reliably. Three practical issues appear together at this resistance level:

• Parasitics dominate. PCB trace, solder-joint, and socket-pin resistance each contribute on the order of 10–50 mΩ. Against a 7.5 Ω target this is a 0.1–0.7% gain error per connection, comparable to or larger than the tolerance of $R_g$ itself.
• Standard values are coarse. Precision E96 resistors below ~10 Ω are rare; available values are quantized in steps that make it hard to land on an arbitrary target gain.
• Temperature drift adds up. The temperature coefficient of the parasitic resistance in series with $R_g$ feeds directly into gain drift, and at single-digit ohms even modest self-heating of the resistor itself shifts the gain measurably.

The remedy is to split the overall amplification between the INA and the summing amplifier, which is the next stage anyway. The first-stage gain still dominates the input-referred noise of the chain, so the INA should provide most of the amplification, but the gain-setting resistor must remain in a range where its value is well-defined. A practical compromise is to choose $G_\text{INA}$ so that $R_g$ lands in the tens-to-hundreds of ohms range.

Select $G_\text{INA} = 500$. The gain-setting resistor is then:

$$R_g = \frac{60\,\text{k}\Omega}{500 - 4} \approx 121\,\Omega \quad (\text{standard E96 value}),$$

and the INA output at full design load is $0.5\,\text{mV} \times 500 = 0.25\,\text{V}$, comfortably below the $\pm 4\,\text{V}$ swing limit. The remaining amplification needed to fill the ADC range (a factor of $5\,\text{V} / 0.25\,\text{V} = 20$) is implemented in the summing amplifier, alongside the offset, at no additional component cost.

Step 2: Design the summing amplifier. The INA output spans $[0\,\text{V},\,0.25\,\text{V}]$ but the ADC expects $[-2.5\,\text{V},\,+2.5\,\text{V}]$. The inverting summing amplifier output is:

$$v_\text{ADC} = -\frac{R_f}{R_a}\,v_\text{INA} - \frac{R_f}{R_b}\,V_\text{offset}.$$

Two conditions fix the two unknowns $R_f/R_a$ and $R_f/R_b$:

• Zero load ($v_\text{INA} = 0\,\text{V}$) must map to $v_\text{ADC} = +2.5\,\text{V}$.
• Full load ($v_\text{INA} = 0.25\,\text{V}$) must map to $v_\text{ADC} = -2.5\,\text{V}$.

Subtracting the two equations gives the signal gain:

$$\frac{R_f}{R_a} = \frac{5.0\,\text{V}}{0.25\,\text{V}} = 20.$$

Using the $-5\,\text{V}$ supply rail as $V_\text{offset}$ and substituting the zero-load condition:

$$-\frac{R_f}{R_b}(-5\,\text{V}) = +2.5\,\text{V} \quad\Longrightarrow\quad R_b = 2\,R_f.$$

The complete transfer function is:

$$v_\text{ADC} = -20\,v_\text{INA} + 2.5\,\text{V}.$$

Verification: at $v_\text{INA} = 0$, $v_\text{ADC} = +2.5\,\text{V}$; at $v_\text{INA} = 0.25\,\text{V}$, $v_\text{ADC} = -20 \times 0.25 + 2.5 = -2.5\,\text{V}$. ✓

The INA contributes a factor of 500, the summing amplifier contributes a magnitude of 20, and the cascaded gain from bridge differential output to ADC input is $500 \times 20 = 10{,}000\,\text{V/V}$. This is the same overall scaling that would have been obtained with $G_\text{INA} = 8000$ and a summing-amp gain of $-1.25$, just distributed across the two stages to keep every component value in a manufacturable range.

Step 3: Effective resolution. The signal now spans the full 5 V ADC input range across 4096 levels:

$$\Delta = \frac{5\,\text{V}}{4096} \approx 1.2\,\text{mV per count},$$

corresponding to a weight resolution of:

$$\frac{500\,\text{g}}{4096} \approx 0.12\,\text{g per count}.$$

This is the theoretical limit imposed by the ADC. Noise, component tolerances, and load cell non-linearity will raise the practical resolution floor above this value.

Anti-Alias Filtering

The signal chain needs one more stage before the ADC. The Nyquist sampling theorem requires that any signal applied to a sampler be band-limited to less than half the sampling rate. Frequency content above $f_s/2$ does not simply disappear: it folds back into the baseband as aliased noise that is indistinguishable from the signal of interest and cannot be removed by any amount of digital processing. A low-pass filter placed immediately before the ADC is therefore mandatory in any practical measurement system, and is called an anti-alias filter.

In a bridge-based measurement, the most consequential out-of-band signal is the 60 Hz power-line interference that couples capacitively into the load cell wiring and onto the breadboard ground rails. The INA125 has a gain-bandwidth product of approximately 600 kHz, so at a gain of $G_\text{INA} = 500$ the closed-loop bandwidth is roughly 1.2 kHz. This is more than wide enough for the slowly varying force signal, but it does nothing to reject 60 Hz interference. Whatever 60 Hz energy reaches the INA inputs is amplified along with the signal and arrives at the ADC unattenuated.

A passive RC low-pass filter followed by a unity-gain op-amp buffer, placed between the summing amplifier output and the ADC input, rejects this interference. The first-order magnitude response is:

$$\left| H(f) \right| = \frac{1}{\sqrt{1 + (f/f_c)^2}},$$

so the 60 Hz attenuation in decibels is:

$$A_{60} = -20 \log_{10}\!\sqrt{1 + (60/f_c)^2}.$$

A cutoff frequency in the range $f_c = 2$ to $10\,\text{Hz}$ is the standard choice for low-frequency sensor electronics. At $f_c = 5\,\text{Hz}$ the 60 Hz attenuation is $-21.6\,\text{dB}$, a factor of 12 reduction in interference amplitude.

The cutoff cannot be lowered without limit. A first-order RC filter settles to within 2% of its final value in approximately four time constants, or $4 / (2\pi f_c)$ seconds. At $f_c = 5\,\text{Hz}$ this is about 130 ms, fast enough for a weighing application but visibly sluggish at lower cutoffs. The cutoff therefore reflects a trade-off: lower values reject more 60 Hz interference but slow the response of the instrument to a new load.

The unity-gain buffer that follows the RC network is not optional. The ADC presents a finite input impedance to whatever drives it; without isolation, this impedance forms part of the filter's load and shifts the cutoff frequency away from the designed value. A single op-amp wired as a voltage follower restores ideal voltage-source behavior at the filter output and decouples the filter design from the ADC's input characteristics.

Design Priorities

Several practical considerations guide signal chain design.

Set the INA gain first, but leave headroom. The INA's first-stage gain dominates the input-referred noise of the whole signal chain, so make it large, but stop short of the output-swing limit. Pushing the INA gain that high forces the gain-setting resistor $R_g$ down into the single-ohm range, where PCB and contact resistance, standard-value granularity, and temperature drift all become meaningful error sources. Keep $R_g$ in the tens-to-hundreds of ohms range and put the remainder of the required gain in the summing amplifier, which is already in the signal path for level shifting.

Check the output swing against the supply. On a split $\pm 5\,\text{V}$ supply, the INA125 output swing is approximately $\pm 4\,\text{V}$. Select the gain so that the full-scale output remains within this limit.

Configure the reference pin correctly. On a split supply, the INA125 reference pin (IAref, pin 5) must be connected to ground. This sets the output at zero load to approximately 0 V, enabling symmetric operation around ground.

Use the summing amplifier for offset and scale. Fine-tuning the gain and offset in the analog domain before the ADC is more efficient than attempting to correct for a poorly scaled signal in software. Each bit of resolution lost due to a mismatched signal chain requires doubling the number of ADC samples to recover the same noise floor by averaging.

Match the ADC supply. Where possible, use the ADC supply as the bridge reference $V_{\text{ref}}$. This ratiometric connection causes supply voltage variations to affect both the bridge output and the ADC reference equally, so their ratio, and therefore the measurement reading, remains stable.

Include an anti-alias filter before the ADC. Any signal entering an ADC must be band-limited below half the sampling rate to prevent out-of-band content from aliasing into the measurement. A first-order RC low-pass filter with a cutoff in the 2 to 10 Hz range rejects 60 Hz power-line interference and easily satisfies the Nyquist condition for any practical ADC sampling rate. Always follow the RC network with a unity-gain op-amp buffer so the ADC input impedance does not shift the filter cutoff.

Protect the ADC inputs. A resistor in series with the ADC input and two diodes to the supply and ground rails limits the voltage seen by the ADC in the event of an overload. This is standard practice in any interface between a high-gain analog chain and an ADC.

Chapter Summary

This chapter developed the amplifier chain needed to connect a resistive sensor to a digital measurement system. The single op-amp difference amplifier provides differential gain but suffers from finite input impedance and sensitivity to resistor matching. The Wheatstone bridge converts a resistance change into a small differential voltage while a common-mode voltage of approximately $V_{\text{ref}}/2$ appears on both output terminals. The three-op-amp instrumentation amplifier solves both limitations of the single op-amp circuit: its input impedance is ideally infinite, its differential gain is set by a single resistor $R_g$, and its CMRR is determined by the precision of the on-chip output stage resistors. A summing amplifier that follows the INA removes the DC offset and scales the signal to fill the ADC input range, maximizing effective resolution. The chain ends with a first-order RC low-pass anti-alias filter and a unity-gain buffer that band-limit the signal below the Nyquist frequency and reject 60 Hz power-line interference before the ADC samples it.